AMD Fam15: Add SPD read functions to wrapper code

Change:
This is the initial step for moving the AMD F15 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Dinar, and was changed to
use the devicetree.cb structures.  Significant cleanup and magic
number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBus initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2777
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

4 files changed, 334 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc
index 7fca122893..4a754995eb 100644
--- a/src/northbridge/amd/agesa/family15/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15/Makefile.inc
@@ -17,4 +17,6 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
+romstage-y += dimmSpd.c
+
 ramstage-y += northbridge.c
diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h
new file mode 100644
index 0000000000..66c44c4b06
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/chip.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _NB_AGESA_CHIP_H_
+#define _NB_AGESA_CHIP_H_
+
+struct northbridge_amd_agesa_family15_config
+{
+	/*
+	 * Here are a couple of examples of how this would be put into the
+	 * devicetree.cb file.  Note the array is oversized to support different
+	 * configurations of server boards.
+	 * This should be placed after the device pci 18.x statements.
+	 *
+	 * Example: AMD Dinar
+	 * register "spdAddrLookup" = "
+	 * { // Use 8-bit SPD addresses here
+	 * 	{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3
+	 * 	{ {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3
+	 * }"
+	 * Example: Tyan S8226
+	 * register "spdAddrLookup" = "
+	 * { // Use 8-bit SPD addresses here
+	 *  { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0
+	 *  { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1
+	 * }"
+	 *
+	 */
+
+	u8 spdAddrLookup[8][4][4];
+};
+
+#endif
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c
new file mode 100644
index 0000000000..294454c387
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/dimmSpd.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <device/pci_def.h>
+#include <device/device.h>
+#include <stdlib.h>
+#include "OEM.h"		/* SMBUS0_BASE_ADDRESS */
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+#include "chip.h"
+
+/* uncomment for source level debug - GDB gets really confused otherwise. */
+//#pragma optimize ("", off)
+
+/**
+ * Read a single SPD byte.  If the first byte is being read, set up the
+ * address and offset. Following bytes auto increment.
+ */
+static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
+						   int offset, int initial_offset)
+{
+	unsigned int status = -1;
+	UINT64 time_limit;
+
+	/* clear status register */
+	__outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
+	__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
+
+	if (offset == initial_offset) {
+		/* Set offset, set slave address and start reading */
+		__outbyte(iobase + SMBUS_CONTROL_REG, offset);
+		__outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
+		__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
+	} else {
+		/* Issue read command - auto increments to next byte */
+		__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
+	}
+	/* time limit to avoid hanging for unexpected error status */
+	time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
+	while (__rdtsc() <= time_limit) {
+		status = __inbyte(iobase + SMBUS_STATUS_REG);
+		if ((status & SMBUS_INTERRUPT_MASK) == 0)
+			continue;	/* SMBusInterrupt not set, keep waiting */
+		if ((status & HOSTBUSY_MASK) != 0)
+			continue;	/* HostBusy set, keep waiting */
+		break;
+	}
+
+	if (status != STATUS__COMPLETED_SUCCESSFULLY)
+		return AGESA_ERROR;
+
+	buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
+	return AGESA_SUCCESS;
+}
+
+/**
+ * Write a single smbus byte.
+ */
+UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer,
+					 int offset)
+{
+	unsigned int status = -1;
+	UINT64 time_limit;
+
+	/* clear status register */
+	__outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
+	__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
+
+	/* set offset, set slave address, set data and start writing */
+	__outbyte(iobase + SMBUS_CONTROL_REG, offset);
+	__outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT));
+	__outbyte(iobase + SMBUS_DATA0_REG, buffer);
+	__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND);
+
+	/* time limit to avoid hanging for unexpected error status */
+	time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
+	while (__rdtsc() <= time_limit) {
+		status = __inbyte(iobase + SMBUS_STATUS_REG);
+		if ((status & SMBUS_INTERRUPT_MASK) == 0)
+			continue;	/* SMBusInterrupt not set, keep waiting */
+		if ((status & HOSTBUSY_MASK) != 0)
+			continue;	/* HostBusy set, keep waiting */
+		break;
+	}
+
+	if (status != STATUS__COMPLETED_SUCCESSFULLY)
+		return AGESA_ERROR;
+
+	return AGESA_SUCCESS;
+}
+
+static void setupFch(UINT16 ioBase)
+{
+	AMD_CONFIG_PARAMS         StdHeader;
+	UINT32                    PciData32;
+	UINT8                     PciData8;
+	PCI_ADDR                  PciAddress;
+
+	/* Set SMBus MMIO. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
+	PciData32 = (ioBase & 0xFFFFFFF0) | BIT0;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
+
+	/* Enable SMBus MMIO. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
+	LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
+	PciData8 |= BIT0;
+	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
+
+	/* Set SMBus clock to 400 KHz */
+	__outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
+}
+
+/**
+ * Read one or more SPD bytes from a DIMM.
+ * Start with offset zero and read sequentially.
+ * Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
+					 UINT16 count)
+{
+	UINT16 index;
+	UINT8 status;
+	UINT8 initial_offset = 0;
+
+	setupFch(iobase);
+
+	for (index = initial_offset; index < count; index++) {
+		status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
+				initial_offset);
+		if (status != AGESA_SUCCESS)
+			return status;
+	}
+
+	return status;
+}
+
+/**
+ * Gets the SMBus address for an SPD from the array in devicetree.cb
+ * then read the SPD into the supplied buffer.
+ */
+AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr)
+{
+	UINT8 spdAddress;
+	AGESA_READ_SPD_PARAMS *info = infoptr;
+	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = NULL;
+
+	if ((dev == 0) || (dev->chip_info == 0))
+		return AGESA_ERROR;
+
+	config = dev->chip_info;
+	if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
+		return AGESA_ERROR;
+	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
+		return AGESA_ERROR;
+	if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
+		return AGESA_ERROR;
+
+	spdAddress = config->spdAddrLookup
+		[info->SocketId][info->MemChannelId][info->DimmId];
+
+	if (spdAddress == 0)
+		return AGESA_ERROR;
+
+	return readspd(SMBUS0_BASE_ADDRESS, spdAddress, (void *)info->Buffer, 256);
+}
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.h b/src/northbridge/amd/agesa/family15/dimmSpd.h
new file mode 100644
index 0000000000..167b4a1034
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/dimmSpd.h
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define READ_BIT				0x01
+
+#define SMBUS_INTERRUPT_MASK	0x02
+#define HOSTBUSY_MASK			0x01
+
+#define SMBUS_READ_BYTE_COMMAND	0x48
+#define SMBUS_READ_COMMAND		0x44
+
+#define SMBUS_WRITE_BYTE_COMMAND	0x48
+
+#define MAX_READ_TSC_COUNT		(2000000000 / 10)
+
+#define PMIO_INDEX_REG			0xCD6
+#define PMIO_DATA_REG			0xCD7
+
+#define SMBUS_BAR_LOW_BYTE		0x2C
+#define SMBUS_BAR_HIGH_BYTE		0x2D
+
+#define SMBUS_STATUS_REG		0x00
+#define SMBUS_SLAVE_STATUS_REG	0x01
+#define SMBUS_COMMAND_REG		0x02
+#define SMBUS_CONTROL_REG		0x03
+#define SMBUS_HOST_CMD_REG		0x04
+#define SMBUS_DATA0_REG			0x05
+#define SMBUS_CLOCK_REG			0x0E
+
+#define STATUS__COMPLETED_SUCCESSFULLY	0x02
+
+#define SMBUS_FREQUENCY_CONST	66000000 / 4
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData);
+
+/*
+ * This function prototype is only used by the AMD Dinar mainboard.  The SMBus
+ * write is used to select which socket's SPD will be read by the subsequent
+ * SPD read call.  This function is being placed in the F15 wrapper code with
+ * the other SPD read functions because the next step of the SPD read clean-up
+ * will be to move the SMBus read/write functions into the southbridge to make
+ * them more generic.  Having the writeSmbusByte() function in the same file as
+ * the readSmbusByte() function will ensure that the writeSmbusByte() function
+ * is not overlooked.
+ */
+UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset);
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif