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authorIonela Voinescu <ionela.voinescu@imgtec.com>2014-12-08 12:51:09 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-13 12:19:20 +0200
commitfb3ea74f9a1cf6a1e8fa32466457889c965f45ab (patch)
tree6a3b91810ec9b41db0de88eb66ea77ecd7aa0702
parente5d13781e9bb7e065f6f2ea312228590553e0b19 (diff)
downloadcoreboot-fb3ea74f9a1cf6a1e8fa32466457889c965f45ab.tar.xz
pistachio: increase the size of romstage to 36K
This is necessary for the subsequent changes that will add to the size of romstage. BUG=chrome-os-partner:31438 TEST=coreboot builds successfully;tested on Pistachio FPGA BRANCH=none Change-Id: I132215bd44708913d878bbd8b6147bef535b52df Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7 Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233871 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 554ebfc04f..1c7ea9a74c 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -29,7 +29,7 @@ SECTIONS
/* GRAM becomes the SRAM. */
SRAM_START(0x9a000000)
BOOTBLOCK(0x9a000000, 16K)
- ROMSTAGE(0x9a004000, 32K)
+ ROMSTAGE(0x9a004000, 36K)
STACK(0x9a01c000, 8K)
PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
SRAM_END(0x9a020000)