fill_pei_ram_data

3 files changed, 76 insertions, 29 deletions

diff --git a/src/northbridge/intel/haswell/do_raminit_frag.c b/src/northbridge/intel/haswell/do_raminit_frag.c
index 977521394e..5f5e73e64d 100644
--- a/src/northbridge/intel/haswell/do_raminit_frag.c
+++ b/src/northbridge/intel/haswell/do_raminit_frag.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include "pei_data.h"
 #include "pei_usb.h"
+#include "pei_ram.h"
 
 static void io_fffa3c2e(void)
 {
@@ -229,3 +230,26 @@ void load_usb(PEI_USB *pusb, struct pei_data *pd)
 	pusb->xhci_resume_info[1] = 1;
 	pusb->xhci_resume_info[2] = 2;
 }
+
+void fill_pei_ram_data(pei_ram_data *r, struct pei_data *pd);
+void fill_pei_ram_data(pei_ram_data *r, struct pei_data *pd)
+{
+	int i;
+	for (i = 0; i < 4; i++) {
+		r->spd_addresses[i] = pd->spd_addresses[i];
+	}
+	r->mchbar = pd->mchbar;
+	r->dmibar = pd->dmibar;
+	r->epbar = pd->epbar;
+	r->pciexbar = pd->pciexbar;
+	r->smbusbar = pd->smbusbar;
+	r->gdxcbar = 0xfed84000;
+	r->tseg_size = pd->tseg_size;
+	r->system_type = pd->system_type;
+	r->v1 = 1;
+	r->edrambar = 0xfed80000;
+	r->ied_region_size = 0x400000;
+	for (i = 0; i < 5; i++) {
+		r->padding[i] = 0;
+	}
+}
diff --git a/src/northbridge/intel/haswell/mrc.asm b/src/northbridge/intel/haswell/mrc.asm
index 5ba0e74b80..354f93fc78 100644
--- a/src/northbridge/intel/haswell/mrc.asm
+++ b/src/northbridge/intel/haswell/mrc.asm
@@ -153,6 +153,7 @@ extern io_fffa476b
 extern io_fffa49a0
 extern io_fffa4c0d
 extern load_usb
+extern fill_pei_ram_data
 
 ;; mrc_wdt
 
@@ -2526,10 +2527,14 @@ mov byte [ebp - 0x2c6], 3
 mov byte [ebp - 0x2b8], 0xff
 rep stosd  ; rep stosd dword es:[edi], eax
 mov al, dl
-lea edi, [ebp - 0x492]
-mov cl, 0x2f
 mov byte [ebp - 0x2b7], 0xff
-rep stosb  ; rep stosb byte es:[edi], al
+
+push dword [ebp - 0x63c]
+lea edi, [ebp - 0x492]
+push edi
+call fill_pei_ram_data
+add esp, 8
+
 mov ecx, dword [ebp - 0x63c]
 mov byte [ebp - 0x2b6], 0xff
 mov byte [ebp - 0x2b5], 0xff
@@ -2538,12 +2543,7 @@ mov byte [ebp - 0x2b3], 0xff
 mov byte [ebp - 0x2b2], 0xff
 mov byte [ebp - 0x2b1], 0xff
 mov byte [ebp - 0x2b0], 0xff
-mov al, byte [ecx + 0x3a]
 mov byte [ebp - 0x2af], 0xff
-mov byte [ebp - 0x492], al
-mov al, byte [ecx + 0x3b]
-mov byte [ebp - 0x491], al
-mov al, byte [ecx + 0x3c]
 mov byte [ebp - 0x2ae], 0xff
 mov byte [ebp - 0x2ad], 0xff
 mov byte [ebp - 0x2ac], 0xff
@@ -2561,34 +2561,14 @@ mov byte [ebp - 0x27b], 1
 mov byte [ebp - 0x462], 1
 mov byte [ebp - 0x461], 1
 mov byte [ebp - 0x460], 1
-mov byte [ebp - 0x490], al
-mov al, byte [ecx + 0x3d]
 lea edi, [ebp - 0x575]
-mov byte [ebp - 0x48f], al
-mov eax, dword [ecx + 4]
-mov dword [ebp - 0x48e], eax
-mov eax, dword [ecx + 8]
-mov dword [ebp - 0x48a], eax
-mov eax, dword [ecx + 0xc]
-mov dword [ebp - 0x486], eax
-mov eax, dword [ecx + 0x10]
-mov dword [ebp - 0x482], eax
 mov esi, mrc_wdt_ppi
-movzx eax, word [ecx + 0x14]
-mov dword [ebp - 0x47a], 0xfed84000
-mov dword [ebp - 0x47e], eax
-mov eax, dword [ecx + 0x36]
-mov dword [ebp - 0x476], eax
-mov eax, dword [ecx + 0x32]
-mov byte [ebp - 0x472], al
 mov ecx, 4
 mov eax, ebx
-mov byte [ebp - 0x471], 1
 rep stosd  ; rep stosd dword es:[edi], eax
 mov al, dl
 lea edi, [ebp - 0x526]
 mov cl, 0x1e
-mov dword [ebp - 0x470], 0xfed80000
 rep stosb  ; rep stosb byte es:[edi], al
 mov ecx, dword [ebp - 0x63c]
 lea eax, [ebp - 0x492]
@@ -2609,7 +2589,6 @@ mov dword [ebp - 0x511], eax
 lea edi, [ebp - 0x600]
 mov al, dl
 mov cl, 5
-mov dword [ebp - 0x467], 0x400000
 mov byte [ebp - 0x526], 0xe
 mov dword [ebp - 0x616], pei_choose_ranges
 mov dword [ebp - 0x612], pei_get_platform_memsize
diff --git a/src/northbridge/intel/haswell/pei_ram.h b/src/northbridge/intel/haswell/pei_ram.h
new file mode 100644
index 0000000000..eb564f5310
--- /dev/null
+++ b/src/northbridge/intel/haswell/pei_ram.h
@@ -0,0 +1,44 @@
+struct _pei_ram_data
+{
+	uint8_t spd_addresses[4];
+	uint32_t mchbar; /* 0x04 */
+	uint32_t dmibar; /* 0x08 */
+	uint32_t epbar; /* 0x0c */
+	uint32_t pciexbar; /* 0x10 */
+	uint32_t smbusbar; /* 0x14 */
+	uint32_t gdxcbar; // 0x18 in coreboot, GDXC_BASE_ADDRESS is 0xfed84000
+	uint32_t tseg_size; // 0x1c
+	uint8_t system_type; // 0x20
+	uint8_t v1;
+	uint32_t edrambar; // 0x22 in coreboot, EDRAM_BASE_ADDRESS is 0xfed80000
+	uint8_t padding[5];
+	uint32_t ied_region_size; // in coreboot, IED_REGION_SIZE is 0x400000
+} __packed;
+
+typedef struct _pei_ram_data pei_ram_data;
+
+/* FIXME: not completed yet, do not use! */
+struct _pei_ram_param
+{
+	uint8_t v0; // 0x00
+	uint16_t max_ddr3_freq; // 0x01
+	uint8_t v1; // 0x03
+	uint8_t padding0[13]; // 0x04
+	uint8_t v2; // 0x11
+	uint8_t padding1[18]; // 0x12
+	uint8_t v3; // 0x24
+	uint8_t padding2[5]; // 0x25
+	uint8_t chan0_disabled; // 0x2a
+	uint8_t chan1_disabled; // 0x2b
+	uint8_t param0[43]; // 0x2c
+	uint32_t dq_pins_interleaved; // 0x57
+	uint8_t param1[10]; // 0x5b
+	uint32_t param2; // 0x65
+	uint16_t padding3; // 0x69
+	uint8_t v4; // 0x6b
+	uint8_t padding4; // 0x6c
+	uint8_t ddr_refresh_2x; // 0x6d
+	uint8_t v5; // 0x6f
+	uint16_t param3; // 0x70
+
+};