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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-01 21:20:33 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:12:53 +0000 |
| commit | 28bca0546bad84291de56d5f7330cd6b9e57c3a3 (patch) | |
| tree | 926d0fb1448d2be8e8eaad952863d8f76d239a5e | |
| parent | 6d13a0a78a03d24c7e390b44d54d1be3fd3fb51c (diff) | |
| download | coreboot-28bca0546bad84291de56d5f7330cd6b9e57c3a3.tar.xz | |
nb/intel/nehalem: Disable PEG and IGD based on devicetree
Tested on Thinkpad X201: PEG device hidden.
Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/lenovo/x201/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/packardbell/ms2290/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/nehalem.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 25 |
4 files changed, 26 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index bf74d710bb..de6d568dd8 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -48,6 +48,7 @@ chip northbridge/intel/nehalem device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 end + device pci 01.0 off end # PEG device pci 02.0 on # VGA controller subsystemid 0x17aa 0x215a end diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bb4e854e59..c98f9a36bc 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -48,6 +48,7 @@ chip northbridge/intel/nehalem device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 end + device pci 01.0 off end # PEG device pci 02.0 on # VGA controller subsystemid 0x1025 0x0379 end diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index f3b9dbbd7d..53743ec9e9 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -67,8 +67,6 @@ typedef struct { #define D0F0_MCHBAR_HI 0x4c #define D0F0_GGC 0x52 #define D0F0_DEVEN 0x54 -/* Note: Intel's datasheet is broken. Assume the following values are correct */ -#define DEVEN_PEG60 (1 << 13) #define DEVEN_IGD (1 << 3) #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0) diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 7b9283fb90..6ec76e1443 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -229,6 +229,28 @@ static void northbridge_init(struct device *dev) northbridge_dmi_init(dev); } +/* Disable unused PEG devices based on devicetree before PCI enumeration */ +static void nehalem_init(void *const chip_info) +{ + u32 deven_mask = UINT32_MAX; + const struct device *dev; + + dev = pcidev_on_root(1, 0); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG10.\n"); + deven_mask &= ~DEVEN_PEG10; + } + dev = pcidev_on_root(2, 0); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling IGD.\n"); + deven_mask &= ~DEVEN_IGD; + } + const struct device *const d0f0 = pcidev_on_root(0, 0); + if (d0f0) + pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); + +} + static struct pci_operations intel_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -269,5 +291,6 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_intel_nehalem_ops = { CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, + .init = nehalem_init, }; |