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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-25 12:00:39 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-28 06:38:10 +0000 |
| commit | 3b1a42f95d3f259f18b5f211dd112d03df9f78dd (patch) | |
| tree | e7afaac2cd1c336719089df35b5b347b29654906 | |
| parent | afc63844e2b889f746163914afe3733c8b4ae1b4 (diff) | |
| download | coreboot-3b1a42f95d3f259f18b5f211dd112d03df9f78dd.tar.xz | |
mb/google/hatch: Enable LPC/eSPI controller
Enable LPC/eSPI controller(D31:F0). EC would be using
eSPI interface, since the strap GPP_C5 is pulled up.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 3cdc3e01a1..164c842485 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -96,7 +96,7 @@ chip soc/intel/cannonlake end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 off end # LPC/eSPI + device pci 1f.0 on end # LPC/eSPI device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA |