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| author | Sven Schnelle <svens@stackframe.org> | 2011-10-18 07:58:10 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-19 00:09:23 +0200 |
| commit | 5563959b0966284341e27e0b1eab3a7353c81673 (patch) | |
| tree | 4a2a99aa2eb770ccf10f9d2a292daa295066c0a8 | |
| parent | 19fd2112f777054d9cfb4999ed9616d3460eaa76 (diff) | |
| download | coreboot-5563959b0966284341e27e0b1eab3a7353c81673.tar.xz | |
I945: replace #if defined() by #if
config.h defines also unset config options (as "0") so #ifdef
matches both settings, which isn't what we want.
Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/293
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 197c58fce5..14c66c4e21 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -91,7 +91,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#if CONFIG_NORTHBRIDGE_INTEL_I945GC printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } @@ -140,7 +140,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } |