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| author | Idwer Vollering <vidwer@gmail.com> | 2014-03-11 15:36:21 +0000 |
|---|---|---|
| committer | Idwer Vollering <vidwer@gmail.com> | 2014-03-16 21:42:49 +0100 |
| commit | 5809a7395d49122757a0ebdfa120e023ebe876ba (patch) | |
| tree | c178320e69a870cae3a6f94d0547aa40ced3ac2e | |
| parent | c078094f39d8683b9a1087dc7f60e8605733ed99 (diff) | |
| download | coreboot-5809a7395d49122757a0ebdfa120e023ebe876ba.tar.xz | |
Make POST device configurable.
Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4561
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
| -rw-r--r-- | src/console/Kconfig | 45 | ||||
| -rw-r--r-- | src/console/post.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/include/cpu/x86/post_code.h | 4 |
4 files changed, 37 insertions, 20 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig index bb64f29587..d77bb9e4c7 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -303,16 +303,6 @@ config NO_POST bool "Don't show any POST codes" default n - -config CONSOLE_POST - bool "Show POST codes on the debug console" - depends on !NO_POST - default n - help - If enabled, coreboot will additionally print POST codes (which are - usually displayed using a so-called "POST card" ISA/PCI/PCI-E - device) on the debug console. - config CMOS_POST bool "Store post codes in CMOS for debugging" depends on !NO_POST && PC80_SYSTEM @@ -339,15 +329,42 @@ config CMOS_POST_EXTRA This will enable extra logging of work that happens between post codes into CMOS for debug. This uses an additional 8 bytes of CMOS. -config IO_POST +config POST_IO + bool "Show POST codes on the debug console" + depends on !NO_POST + default n + help + If enabled, coreboot will additionally print POST codes (which are + usually displayed using a so-called "POST card" ISA/PCI/PCI-E + device) on the debug console. + +config POST_DEVICE + bool "Send POST codes to an external device" + depends on !NO_POST + default y + +choice + prompt "Device to send POST codes to" + depends on POST_DEVICE + default POST_DEVICE_NONE + +config POST_DEVICE_NONE + bool "None" +config POST_DEVICE_LPC + bool "LPC" +config POST_DEVICE_PCI_PCIE + bool "PCI/PCIe" +endchoice + +config POST_IO bool "Send POST codes to an IO port" - depends on PC80_SYSTEM + depends on PC80_SYSTEM && !NO_POST default y help If enabled, POST codes will be written to an IO port. -config IO_POST_PORT - depends on IO_POST +config POST_IO_PORT + depends on POST_IO hex "IO port for POST codes" default 0x80 help diff --git a/src/console/post.c b/src/console/post.c index 35cc0e85e1..ef1a3a5a1d 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -161,8 +161,8 @@ void post_code(uint8_t value) #if CONFIG_CMOS_POST cmos_post_code(value); #endif -#if CONFIG_IO_POST - outb(value, CONFIG_IO_POST_PORT); +#if CONFIG_POST_IO + outb(value, CONFIG_POST_IO_PORT); #endif #endif mainboard_post(value); diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc index 61fb1c2636..a269fb9691 100644 --- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc @@ -251,8 +251,8 @@ halt2: .Lhlt: xchg %al, %ah -#if CONFIG_IO_POST - outb %al, $CONFIG_IO_POST_PORT +#if CONFIG_POST_IO + outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) #endif diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index 7465f62332..6acfe106e3 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -2,10 +2,10 @@ #include <console/post_codes.h> -#if CONFIG_IO_POST +#if CONFIG_POST_IO #define post_code(value) \ movb $value, %al; \ - outb %al, $CONFIG_IO_POST_PORT + outb %al, $CONFIG_POST_IO_PORT #else #define post_code(value) |