diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-31 14:47:43 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-31 14:47:43 +0000 |
| commit | 64ed2b73451de4b655b3fdda0ff42825a165c317 (patch) | |
| tree | 0faaae313a9a9edbf8b33f56fc18830ba14aa75f | |
| parent | 5a1f5970857a5ad1fda0cf9d5945192408bf537b (diff) | |
| download | coreboot-64ed2b73451de4b655b3fdda0ff42825a165c317.tar.xz | |
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C
completely?
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
186 files changed, 1279 insertions, 1279 deletions
diff --git a/src/console/console.c b/src/console/console.c index ace76d902c..6b4173c864 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -100,12 +100,12 @@ void __attribute__((noreturn)) die(const char *msg) void console_init(void) { static const char console_test[] = - "\r\n\r\ncoreboot-" + "\n\ncoreboot-" COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD - " starting...\r\n"; + " starting...\n"; print_info(console_test); } @@ -115,7 +115,7 @@ void post_code(u8 value) #if CONFIG_SERIAL_POST==1 print_emerg("POST: 0x"); print_emerg_hex8(value); - print_emerg("\r\n"); + print_emerg("\n"); #endif outb(value, 0x80); #endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 939990997c..b8a7285b89 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -5,7 +5,7 @@ static inline void print_debug_pcar(const char *strval, uint32_t val) { - printk(BIOS_DEBUG, "%s%08x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%08x\n", strval, val); } /* from linux kernel 2.6.32 asm/string_32.h */ @@ -86,10 +86,10 @@ static void post_cache_as_ram(void) /* We can put data to stack again */ /* only global variable sysinfo in cache need to be offset */ - print_debug("Done\r\n"); + print_debug("Done\n"); print_debug_pcar("testx = ", testx); - print_debug("Disabling cache as ram now \r\n"); + print_debug("Disabling cache as ram now \n"); disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); @@ -99,7 +99,7 @@ static void post_cache_as_ram(void) #else memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); #endif - print_debug("Done\r\n"); + print_debug("Done\n"); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); @@ -115,5 +115,5 @@ static void post_cache_as_ram(void) copy_and_run(); /* We will not return */ - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 3a56fdd1c3..42d96c509a 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -109,7 +109,7 @@ unsigned get_apicid_base(unsigned ioapic_num) if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n"); + printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n"); enable_apic_ext_id(nodes); } diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 59cb5460d2..2b23e11c1d 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -15,21 +15,21 @@ static inline void print_debug_fv(const char *str, unsigned val) { #if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x\r\n", str, val); + printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, unsigned val) { #if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%02x\r\n", str, val); + printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2) { #if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2); + printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -131,7 +131,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) apicidx = lapicid(); if (apicid != apicidx) { - printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx); + printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx); return fidvid; } @@ -328,10 +328,10 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) if (showmessage) { if (vid_new != vid_cur) { - print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); + print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); } if (fid_new != fid_cur) { - print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); + print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); } } diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 847a8a7fa6..151eb6f01c 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -16,7 +16,7 @@ static inline void print_initcpu8 (const char *strval, unsigned val) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%02x\n", strval, val); } static inline void print_initcpu8_nocr (const char *strval, unsigned val) @@ -27,12 +27,12 @@ static inline void print_initcpu8_nocr (const char *strval, unsigned val) static inline void print_initcpu16 (const char *strval, unsigned val) { - printk(BIOS_DEBUG, "%s%04x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%04x\n", strval, val); } static inline void print_initcpu(const char *strval, unsigned val) { - printk(BIOS_DEBUG, "%s%08x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%08x\n", strval, val); } typedef void (*process_ap_t)(unsigned apicid, void *gp); @@ -155,7 +155,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid); static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str) { - printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); + printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid); } @@ -201,7 +201,7 @@ static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other t { print_debug("started ap apicid: "); for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); - print_debug("\r\n"); + print_debug("\n"); } static void allow_all_aps_stop(unsigned bsp_apicid) @@ -286,8 +286,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) #endif if (cpu_init_detectedx) { - print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from "); - print_debug("\r\nIssuing SOFT_RESET...\r\n"); + print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from "); + print_debug("\nIssuing SOFT_RESET...\n"); soft_reset(); } @@ -351,7 +351,7 @@ static void wait_all_core0_started(void) while(!is_core0_started(i)) {} print_initcpu8_nocr(" ", i); } - print_debug("\r\n"); + print_debug("\n"); } diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c index ac8b7b1f66..a80c0922c0 100644 --- a/src/cpu/amd/model_lx/cpureginit.c +++ b/src/cpu/amd/model_lx/cpureginit.c @@ -209,9 +209,9 @@ void SetDelayControl(void) print_debug_hex32(msr.hi); print_debug(" and lo "); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); wrmsr(GLCP_DELAY_CONTROLS, msr); - print_debug("SetDelayControl done\r\n"); + print_debug("SetDelayControl done\n"); return; } @@ -225,7 +225,7 @@ void cpuRegInit(void) /* Castle 2.0 BTM periodic sync period. */ /* [40:37] 1 sync record per 256 bytes */ - print_debug("Castle 2.0 BTM periodic sync period.\r\n"); + print_debug("Castle 2.0 BTM periodic sync period.\n"); msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); msr.hi |= (0x8 << 5); @@ -235,7 +235,7 @@ void cpuRegInit(void) * LX performance setting. * Enable Quack for fewer re-RAS on the MC */ - print_debug("Enable Quack for fewer re-RAS on the MC\r\n"); + print_debug("Enable Quack for fewer re-RAS on the MC\n"); msrnum = GLIU0_ARB; msr = rdmsr(msrnum); msr.hi &= ~ARB_UPPER_DACK_EN_SET; @@ -251,25 +251,25 @@ void cpuRegInit(void) /* GLIU port active enable, limit south pole masters * (AES and PCI) to one outstanding transaction. */ - print_debug(" GLIU port active enable\r\n"); + print_debug(" GLIU port active enable\n"); msrnum = GLIU1_PORT_ACTIVE; msr = rdmsr(msrnum); msr.lo &= ~0x880; wrmsr(msrnum, msr); /* Set the Delay Control in GLCP */ - print_debug("Set the Delay Control in GLCP\r\n"); + print_debug("Set the Delay Control in GLCP\n"); SetDelayControl(); /* Enable RSDC */ - print_debug("Enable RSDC\r\n"); + print_debug("Enable RSDC\n"); msrnum = CPU_AC_SMM_CTL; msr = rdmsr(msrnum); msr.lo |= SMM_INST_EN_SET; wrmsr(msrnum, msr); /* FPU imprecise exceptions bit */ - print_debug("FPU imprecise exceptions bit\r\n"); + print_debug("FPU imprecise exceptions bit\n"); msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); msr.lo |= FPU_IE_SET; @@ -277,14 +277,14 @@ void cpuRegInit(void) /* Power Savers (Do after BIST) */ /* Enable Suspend on HLT & PAUSE instructions */ - print_debug("Enable Suspend on HLT & PAUSE instructions\r\n"); + print_debug("Enable Suspend on HLT & PAUSE instructions\n"); msrnum = CPU_XC_CONFIG; msr = rdmsr(msrnum); msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; wrmsr(msrnum, msr); /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ - print_debug("Enable SUSP and allow TSC to run in Suspend\r\n"); + print_debug("Enable SUSP and allow TSC to run in Suspend\n"); msrnum = CPU_BC_CONF_0; msr = rdmsr(msrnum); msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; @@ -302,10 +302,10 @@ void cpuRegInit(void) #endif /* Setup throttling delays to proper mode if it is ever enabled. */ - print_debug("Setup throttling delays to proper mode\r\n"); + print_debug("Setup throttling delays to proper mode\n"); msrnum = GLCP_TH_OD; msr.hi = 0; msr.lo = 0x00000603C; wrmsr(msrnum, msr); - print_debug("Done cpuRegInit\r\n"); + print_debug("Done cpuRegInit\n"); } diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index 4f5c68efd5..48917e3d1d 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num) if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); + printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n"); enable_apic_ext_id(sysconf.nodes); } diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index f52e8fe622..711614a5b8 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -248,14 +248,14 @@ udelay(int microseconds) { static void dumpram(void){ - print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n"); - print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n"); - print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n"); - - print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n"); - print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n"); - print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n"); - print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n"); + print_err("ctl "); print_err_hex8(*drcctl); print_err("\n"); + print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n"); + print_err("cfg "); print_err_hex8(*drccfg); print_err("\n"); + + print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n"); + print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n"); + print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n"); + print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n"); } /* there is a lot of silliness in the amd code, and it is @@ -311,11 +311,11 @@ int sizemem(void) print_err("NOP\n"); /* 100? 200? */ udelay(100); - print_err("after sc520_udelay\r\n"); + print_err("after sc520_udelay\n"); /* issue all banks precharge */ *drcctl=0x02; - print_err("set *drcctl to 2 \r\n"); + print_err("set *drcctl to 2 \n"); dummy_write(); print_err("PRE\n"); @@ -334,7 +334,7 @@ int sizemem(void) *drcctl=0x04; for (i=0; i<8; i++) /* refresh 8 times */{ dummy_write(); - print_err("dummy write\r\n"); + print_err("dummy write\n"); } print_err("8 dummy writes\n"); @@ -342,18 +342,18 @@ int sizemem(void) *drcctl=0x00; print_err("normal\n"); - print_err("HI done normal\r\n"); + print_err("HI done normal\n"); print_err("sizemem\n"); for(bank = 3; bank >= 0; bank--) { - print_err("Try to assign to l\r\n"); + print_err("Try to assign to l\n"); *lp = 0xdeadbeef; - print_err("assigned l ... \r\n"); + print_err("assigned l ... \n"); if (*lp != 0xdeadbeef) { print_err(" no memory at bank "); // print_err_hex8(bank); // print_err(" value "); print_err_hex32(*lp); - print_err("\r\n"); + print_err("\n"); // continue; } *drcctl = 2; @@ -362,7 +362,7 @@ int sizemem(void) l = *drcbendadr; l >>= 8; *drcbendadr = l; - print_err("loop around\r\n"); + print_err("loop around\n"); *drcctl = 0; dummy_write(); } @@ -386,11 +386,11 @@ int sizemem(void) print_err("NOP\n"); /* 100? 200? */ //sc520_udelay(100); - print_err("after sc520_udelay\r\n"); + print_err("after sc520_udelay\n"); /* issue all banks precharge */ *drcctl=0x02; - print_err("set *drcctl to 2 \r\n"); + print_err("set *drcctl to 2 \n"); dummy_write(); print_err("PRE\n"); @@ -409,7 +409,7 @@ int sizemem(void) *drcctl=0x04; for (i=0; i<8; i++) /* refresh 8 times */{ dummy_write(); - print_err("dummy write\r\n"); + print_err("dummy write\n"); } print_err("8 dummy writes\n"); @@ -417,7 +417,7 @@ int sizemem(void) *drcctl=0x00; print_err("normal\n"); - print_err("HI done normal\r\n"); + print_err("HI done normal\n"); bank = 3; @@ -558,7 +558,7 @@ print_err("4b\n"); al -= i&3; *drcbendaddr = rows >> al; print_err("computed ending_adr = "); print_err_hex8(ending_adr); - print_err("\r\n"); + print_err("\n"); */ bad_reinit: @@ -592,7 +592,7 @@ bad_reinit: return bank; bad_ram: - print_info("bad ram!\r\n"); + print_info("bad ram!\n"); /* you are here because the read-after-write failed, * in most cases because: no ram in that bank! * set badbank to 1 and go to reinit @@ -600,7 +600,7 @@ bad_ram: ending_adr = 0; goto bad_reinit; while(1) - print_err("DONE NEXTBANK\r\n"); + print_err("DONE NEXTBANK\n"); #endif } @@ -628,27 +628,27 @@ int staticmem(void) /* two autorefreshes */ *drcctl = 4; *zero = 0; - print_debug("one zero out on refresh\r\n"); + print_debug("one zero out on refresh\n"); *zero = 0; - print_debug("two zero out on refresh\r\n"); + print_debug("two zero out on refresh\n"); /* load mode register */ *drcctl = 3; *zero = 0; - print_debug("DONE the load mode reg\r\n"); + print_debug("DONE the load mode reg\n"); /* normal mode */ *drcctl = 0x0; *zero = 0; - print_debug("DONE one last write and then turn on refresh etc\r\n"); + print_debug("DONE one last write and then turn on refresh etc\n"); *drcctl = 0x18; *zero = 0; - print_debug("DONE the normal\r\n"); + print_debug("DONE the normal\n"); *zero = 0xdeadbeef; if (*zero != 0xdeadbeef) - print_debug("NO LUCK\r\n"); + print_debug("NO LUCK\n"); else - print_debug("did a store and load ...\r\n"); + print_debug("did a store and load ...\n"); //print_err_hex32(*zero); - // print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n"); + // print_err(" zero is now "); print_err_hex32(*zero); print_err("\n"); } diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index a02323dedf..22c3a11503 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -82,7 +82,7 @@ void intel_update_microcode(const void *microcode_updates) print_debug_hex32(pf); print_debug(" rev = 0x"); print_debug_hex32(rev); - print_debug("\r\n"); + print_debug("\n"); m = microcode_updates; for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { @@ -99,7 +99,7 @@ void intel_update_microcode(const void *microcode_updates) print_debug_hex32(new_rev); print_debug(" from revision "); print_debug_hex32(rev); - print_debug("\r\n"); + print_debug("\n"); break; } if (m->total_size) { diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c index fa7ab74bbc..40269ba5b3 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c @@ -40,10 +40,10 @@ void stage1_main(unsigned long bist) "movl %%esp, %0\n\t" : "=a" (v_esp) ); - printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp); + printk(BIOS_SPEW, "v_esp=%08x\n", v_esp); } - printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset); + printk(BIOS_SPEW, "cpu_reset = %08x\n",cpu_reset); if(cpu_reset == 0) { print_spew("Clearing initial memory region: "); @@ -83,12 +83,12 @@ void stage1_main(unsigned long bist) #ifdef CONFIG_DEACTIVATE_CAR print_debug("Deactivating CAR"); #include CONFIG_DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); + print_debug(" - Done.\n"); #endif /* Copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); /* We will not return */ } - print_debug("sorry. parachute did not open.\r\n"); + print_debug("sorry. parachute did not open.\n"); } diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index 269758b394..6e43bf834f 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -541,7 +541,7 @@ static void ati_ragexl_init(device_t dev) #endif #if 0 - printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer); + printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer); #endif chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); @@ -561,7 +561,7 @@ static void ati_ragexl_init(device_t dev) return ; found: - printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev); + printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev); #if 0 if (M64_HAS(INTEGRATED)) { /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 448d7b83c3..e7f3c617f5 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -92,16 +92,16 @@ static void print_smbus_regs(struct device *dev) unsigned char byte; status = smbus_read_byte(dev, j); if (status < 0) { - // printk(BIOS_DEBUG, "bad device status= %08x\r\n", status); + // printk(BIOS_DEBUG, "bad device status= %08x\n", status); break; } if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - printk(BIOS_DEBUG, "\r\n"); + printk(BIOS_DEBUG, "\n"); } static void print_smbus_regs_all(struct device *dev) diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index 0caf66e088..8329f08414 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -26,7 +26,7 @@ static void adm1027_enable_monitoring(device_t dev) result = smbus_read_byte(dev, ADM1027_REG_CONFIG1); if (!(result & CFG1_RDY)) { - printk(BIOS_DEBUG, "ADM1027: monitoring not ready\r\n"); + printk(BIOS_DEBUG, "ADM1027: monitoring not ready\n"); return; } result = (result | CFG1_STRT); @@ -34,9 +34,9 @@ static void adm1027_enable_monitoring(device_t dev) result = smbus_read_byte(dev, ADM1027_REG_CONFIG1); if (!(result & CFG1_STRT)) { - printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\r\n"); + printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\n"); } - printk(BIOS_DEBUG, "ADM1027: monitoring enabled\r\n"); + printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } static void adm1027_init(device_t dev) diff --git a/src/include/assert.h b/src/include/assert.h index 3bd6be972d..718f72ebfc 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -29,7 +29,7 @@ print_emerg(__FILE__); \ print_emerg("', line 0x"); \ print_debug_hex32(__LINE__); \ - print_emerg("\r\n"); \ + print_emerg("\n"); \ /* die(""); */ \ } \ } @@ -39,7 +39,7 @@ print_emerg(__FILE__); \ print_emerg("', line 0x"); \ print_debug_hex32(__LINE__); \ - print_emerg("\r\n"); \ + print_emerg("\n"); \ /* die(""); */ \ } diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h index 153b39e22c..7dbd18b125 100644 --- a/src/include/cpu/x86/bist.h +++ b/src/include/cpu/x86/bist.h @@ -10,7 +10,7 @@ static void report_bist_failure(u32 bist) print_emerg("BIST failed: "); print_emerg_hex32(bist); #endif - die("\r\n"); + die("\n"); } } diff --git a/src/lib/debug.c b/src/lib/debug.c index 7eeabdef47..ab7c1f8562 100644 --- a/src/lib/debug.c +++ b/src/lib/debug.c @@ -23,7 +23,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -31,7 +31,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -43,7 +43,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/lib/generic_dump_spd.c b/src/lib/generic_dump_spd.c index b4ff598612..2fe1ea305b 100644 --- a/src/lib/generic_dump_spd.c +++ b/src/lib/generic_dump_spd.c @@ -6,7 +6,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -20,20 +20,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -46,20 +46,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index 79b501f9a4..edecc06850 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -9,7 +9,7 @@ static inline void print_debug_sdram_8(const char *strval, uint32_t val) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "%s%02x\n", strval, val); #else - print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); + print_debug(strval); print_debug_hex8(val); print_debug("\n"); #endif } @@ -48,7 +48,7 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl) * Some chipsets do the work for us while on others * we need to it by hand. */ - print_debug("Ram3\r\n"); + print_debug("Ram3\n"); #if RAMINIT_SYSINFO == 1 sdram_enable(controllers, ctrl, sysinfo); @@ -56,5 +56,5 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl) sdram_enable(controllers, ctrl); #endif - print_debug("Ram4\r\n"); + print_debug("Ram4\n"); } diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index a43101235b..605d555e46 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -52,13 +52,13 @@ static void ram_fill(unsigned long start, unsigned long stop) * Fill. */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop); + printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM fill: "); print_debug_hex32(start); print_debug("-"); print_debug_hex32(stop); - print_debug("\r\n"); + print_debug("\n"); #endif for(addr = start; addr < stop ; addr += 4) { /* Display address being filled */ @@ -74,10 +74,10 @@ static void ram_fill(unsigned long start, unsigned long stop) }; /* Display final address */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "%08lx\r\nDRAM filled\r\n", addr); + printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr); #else print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); + print_debug("\nDRAM filled\n"); #endif } @@ -89,13 +89,13 @@ static void ram_verify(unsigned long start, unsigned long stop) * Verify. */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop); + printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM verify: "); print_debug_hex32(start); print_debug_char('-'); print_debug_hex32(stop); - print_debug("\r\n"); + print_debug("\n"); #endif for(addr = start; addr < stop ; addr += 4) { unsigned long value; @@ -112,20 +112,20 @@ static void ram_verify(unsigned long start, unsigned long stop) if (value != addr) { /* Display address with error */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value); + printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value); #else print_err("Fail: @0x"); print_err_hex32(addr); print_err(" Read value=0x"); print_err_hex32(value); - print_err("\r\n"); + print_err("\n"); #endif i++; if(i>256) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "Aborting.\n\r"); + printk(BIOS_DEBUG, "Aborting.\n"); #else - print_debug("Aborting.\n\r"); + print_debug("Aborting.\n"); #endif break; } @@ -140,17 +140,17 @@ static void ram_verify(unsigned long start, unsigned long stop) if (i) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\nDRAM did _NOT_ verify!\r\n"); + printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); #else - print_debug("\r\nDRAM did _NOT_ verify!\r\n"); + print_debug("\nDRAM did _NOT_ verify!\n"); #endif die("DRAM ERROR"); } else { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\nDRAM range verified.\r\n"); + printk(BIOS_DEBUG, "\nDRAM range verified.\n"); #else - print_debug("\r\nDRAM range verified.\r\n"); + print_debug("\nDRAM range verified.\n"); #endif } } @@ -164,22 +164,22 @@ void ram_check(unsigned long start, unsigned long stop) * are tested. -Tyson */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\r\n", start, stop); + printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop); #else print_debug("Testing DRAM : "); print_debug_hex32(start); print_debug("-"); print_debug_hex32(stop); - print_debug("\r\n"); + print_debug("\n"); #endif ram_fill(start, stop); /* Make sure we don't read before we wrote */ phys_memory_barrier(); ram_verify(start, stop); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "Done.\r\n"); + printk(BIOS_DEBUG, "Done.\n"); #else - print_debug("Done.\r\n"); + print_debug("Done.\n"); #endif } diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index b46ca394be..3c808d41cb 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index a5991ad1eb..3dc2801546 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index f8b64f1320..6cdaf42df5 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x06); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index e9b21ed029..813b009471 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -50,7 +50,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* get module banks (sides) per dimm, SPD byte 5 */ module_banks = spd_read_byte(0xA0, 5); if (module_banks < 1 || module_banks > 2) - print_err("Module banks per dimm\r\n"); + print_err("Module banks per dimm\n"); module_banks >>= 1; msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); @@ -58,7 +58,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* get component banks per module bank, SPD byte 17 */ val = spd_read_byte(0xA0, 17); if (val < 2 || val > 4) - print_err("Component banks per module bank\r\n"); + print_err("Component banks per module bank\n"); val >>= 2; msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); @@ -78,7 +78,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) print_debug("computed msr.hi "); print_debug_hex32(msr.hi); - print_debug("\r\n"); + print_debug("\n"); msr.lo = 0x00003000; wrmsr(MC_CF07_DATA, msr); diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 582e93abc2..c2b8e8c7b3 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -69,7 +69,7 @@ void hardwaremain(int ret_addr) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n"); #else - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); #endif train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index c46bdf447d..b45e4f6716 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -92,14 +92,14 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); } while ((ret!=0) && (i-->0)); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -246,7 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Read FIDVID_STATUS */ msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -276,7 +276,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } #endif diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c index 55c62649c8..0db327c5c6 100644 --- a/src/mainboard/arima/hdama/debug.c +++ b/src/mainboard/arima/hdama/debug.c @@ -23,7 +23,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -31,7 +31,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -43,7 +43,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -70,7 +70,7 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr int n; for(n = 0; n < controllers; n++) { int i; - print_debug("\r\n"); + print_debug("\n"); activate_spd_rom(&ctrl[n]); for(i = 0; i < 4; i++) { unsigned device; @@ -87,13 +87,13 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } #if 0 @@ -104,7 +104,7 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr #endif print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl[n].channel1[i]; if (device) { @@ -119,13 +119,13 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } #if 0 @@ -136,7 +136,7 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr #endif print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 3440e717c0..cdf4b3901a 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index b64ccae0fd..eb8ad4f777 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index c2390c76d1..7f57ddcb1c 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -89,7 +89,7 @@ void soft_reset(void) uint8_t tmp; set_bios_reset(); - print_debug("soft reset \r\n"); + print_debug("soft reset \n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); enable_rom_decode(); - print_info("now booting... fallback\r\n"); + print_info("now booting... fallback\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { @@ -210,7 +210,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); enable_rom_decode(); - print_info("now booting... real_main\r\n"); + print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -222,7 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); - print_info("now booting... Core0 started\r\n"); + print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS==1 /* It is said that we should start core1 after all core0 launched. */ @@ -237,7 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= k8t890_early_setup_ht(); if (needs_reset) { - print_debug("ht reset -\r\n"); + print_debug("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 2514019aa6..5b542a2985 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -105,12 +105,12 @@ void activate_spd_rom(const struct mem_controller *ctrl) /* this function might fail on some K8 CPUs with errata #181 */ static void ldtstop_sb(void) { - print_debug("toggle LDTSTP#\r\n"); + print_debug("toggle LDTSTP#\n"); u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); reg = reg ^ (1 << 0); outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); reg = inb(VT8237R_ACPI_IO_BASE + 0x15); - print_debug("done\r\n"); + print_debug("done\n"); } #include "cpu/amd/model_fxx/fidvid.c" @@ -127,7 +127,7 @@ void soft_reset(void) uint8_t tmp; set_bios_reset(); - print_debug("soft reset \r\n"); + print_debug("soft reset \n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); @@ -188,7 +188,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); enable_rom_decode(); - print_info("now booting... real_main\r\n"); + print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -199,7 +199,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); - print_info("now booting... Core0 started\r\n"); + print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS==1 /* It is said that we should start core1 after all core0 launched. */ @@ -222,9 +222,9 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) if (needs_reset) { print_debug_hex8(needs_reset); - print_debug("Xht reset -\r\n"); + print_debug("Xht reset -\n"); soft_reset(); - print_debug("NO reset\r\n"); + print_debug("NO reset\n"); } @@ -233,7 +233,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) vt8237_sb_enable_fid_vid(); enable_fid_change(); - print_debug("after enable_fid_change\r\n"); + print_debug("after enable_fid_change\n"); init_fidvid_bsp(bsp_apicid); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 2801f9e06a..f1511574d4 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -101,26 +101,26 @@ static void main(unsigned long bist) uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); /* ram_check(0, 640 * 1024); */ - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 71211c587c..37751ce27a 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -70,9 +70,9 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x71 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_send_byte(SMBUS_HUB, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_blast_resource_map(); @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bcm5785_early_setup(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c index 766a819d52..2ea3db32ea 100644 --- a/src/mainboard/dell/s1850/debug.c +++ b/src/mainboard/dell/s1850/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -212,14 +212,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -227,7 +227,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -245,7 +245,7 @@ void show_dram_slots(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); @@ -256,7 +256,7 @@ void show_dram_slots(void) print_debug("present: "); } print_debug_hex8(status); - print_debug("\r\n"); + print_debug("\n"); device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } @@ -269,7 +269,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -279,7 +279,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c index e22ffeef80..50e9e6e7b0 100644 --- a/src/mainboard/dell/s1850/watchdog.c +++ b/src/mainboard/dell/s1850/watchdog.c @@ -52,6 +52,6 @@ static void disable_watchdogs(void) { // disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 4865622181..1814634277 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -80,7 +80,7 @@ static inline void dumpmem(void){ print_err_hex8(c); print_err(" "); } - print_err("\r\n"); + print_err("\n"); } } @@ -190,16 +190,16 @@ static void main(unsigned long bist) uart_init(); console_init(); for(i = 0; i < 100; i++) - print_err("fill usart\r\n"); + print_err("fill usart\n"); // while(1) - print_err("HI THERE!\r\n"); + print_err("HI THERE!\n"); // sizemem(); staticmem(); print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); print_err("\n"); // while(1) - print_err("STATIC MEM DONE\r\n"); + print_err("STATIC MEM DONE\n"); outb(0xee, 0x80); print_err("loop forever ...\n"); @@ -227,12 +227,12 @@ static void main(unsigned long bist) #endif #if 0 - print_err("RAM CHECK!\r\n"); + print_err("RAM CHECK!\n"); // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); #endif #if 0 - print_err("RAM CHECK for 32 MB!\r\n"); + print_err("RAM CHECK for 32 MB!\n"); // Check 32MB of memory @ 0 ram_check(0x00000000, 0x02000000); #endif @@ -243,17 +243,17 @@ static void main(unsigned long bist) for(i = 0; i < 0x20000; i++) { /* print_err("Set dst "); print_err_hex32((unsigned long) dst); - print_err(" to "); print_err_hex32(*src); print_err("\r\n"); + print_err(" to "); print_err_hex32(*src); print_err("\n"); */ *dst = *src; - //print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n"); + //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n"); dst++, src++; outb((unsigned char)i, 0x80); } } dumpmem(); outb(0, 0x80); - print_err("loop forever\r\n"); + print_err("loop forever\n"); outb(0xdd, 0x80); __asm__ volatile( "movl %0, %%edi\n\t" @@ -262,7 +262,7 @@ static void main(unsigned long bist) : "a" (0x4000) ); - print_err("Oh dear, I'm afraid it didn't work...\r\n"); + print_err("Oh dear, I'm afraid it didn't work...\n"); while(1); #endif diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index d0a5eeb351..e42a312400 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -84,7 +84,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index d66bf51f59..7a0d910884 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -215,7 +215,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -241,7 +241,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -265,7 +265,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index 2bd3205842..28f47597e9 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -82,7 +82,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 9ac67e465f..964e8048b3 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -254,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -268,7 +268,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -279,7 +279,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index c70ff27556..f7897db6ee 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -230,7 +230,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -256,7 +256,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); @@ -265,7 +265,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -274,7 +274,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index ab42a7ef9d..cde7fbdc5d 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 9bbad71346..508b751b06 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index 5a24c4a3ca..9aec7aa65e 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -34,7 +34,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -71,52 +71,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -126,7 +126,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -157,7 +157,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -165,7 +165,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -177,7 +177,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -187,7 +187,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -200,14 +200,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -231,7 +231,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -245,20 +245,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -271,20 +271,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -297,13 +297,13 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -311,7 +311,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -329,7 +329,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -338,7 +338,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index 5546421156..b4f2a185b3 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c index d8c694b4af..fb00984b7e 100644 --- a/src/mainboard/intel/jarrell/jarrell_fixups.c +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -58,12 +58,12 @@ static void mainboard_set_e7520_pll(unsigned bits) /* set gpio 42,44 signal levels */ data = inb(gpio_index + PC87427_GPDO_4); if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) { - print_debug("set_pllsel: correct settings detected!\r\n"); + print_debug("set_pllsel: correct settings detected!\n"); return; /* settings already configured */ } else { outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4); /* reset */ - print_debug("set_pllsel: settings adjusted, now resetting...\r\n"); + print_debug("set_pllsel: settings adjusted, now resetting...\n"); // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */ // mch_reset(); full_reset(); diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c index e9008a40dc..567d15c10f 100644 --- a/src/mainboard/intel/jarrell/power_reset_check.c +++ b/src/mainboard/intel/jarrell/power_reset_check.c @@ -6,7 +6,7 @@ static void power_down_reset_check(void) cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; print_debug("Boot byte = "); print_debug_hex8(cmos); - print_debug("\r\n"); + print_debug("\n"); if((cmos>2)&&(cmos&1)) full_reset(); } diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index 29e8ba36f6..90782d9fbf 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -91,7 +91,7 @@ static void disable_watchdogs(void) disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } static void ich5_watchdog_on(void) @@ -134,5 +134,5 @@ static void ich5_watchdog_on(void) value &= ~(1 << 11); outw(value, base + 0x08); - print_debug("Watchdog ICH5 enabled\r\n"); + print_debug("Watchdog ICH5 enabled\n"); } diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 685f3b8700..4c57de1d75 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -86,6 +86,6 @@ static void main(unsigned long bist) // NOTE: ROMCC dies with an internal compiler error // if the following line is removed. - print_debug("SDRAM is up.\r\n"); + print_debug("SDRAM is up.\n"); } diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index fec1020dba..da0cc57af7 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -207,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 3ceef39900..537d987f6a 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -207,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 3ceef39900..537d987f6a 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -207,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index 4de5aa72ab..a0ad339cd9 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -103,26 +103,26 @@ static void main(unsigned long bist) uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); /* ram_check(0, 640 * 1024); */ - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 200f7567bc..753488933e 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index bc097e385d..4c3f615da0 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -24,7 +24,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) msr_t msr; /* 1. Initialize GLMC registers base on SPD values, * Hard coded as XpressROM for now */ - //print_debug("sdram_enable step 1\r\n"); + //print_debug("sdram_enable step 1\n"); msr = rdmsr(0x20000018); msr.hi = 0x10076013; msr.lo = 0x3400; diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 7a73a1b402..344e0eed84 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { print_err("ERROR: spd_read_byte(DIMM0, 0x"); print_err_hex8(address); - print_err(") returns 0xff\r\n"); + print_err(") returns 0xff\n"); } #endif @@ -222,7 +222,7 @@ void cache_as_ram_main(void) if ((err = smc_send_config(SMC_CONFIG))) { print_err("ERROR "); print_err_char('0'+err); - print_err(" sending config data to SMC\r\n"); + print_err(" sending config data to SMC\n"); } sdram_initialize(1, memctrl); diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 2a6c6f368b..ac5487f92c 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index f8ac2fec3a..246d7afc64 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -72,7 +72,7 @@ void hardwaremain(int ret_addr) */ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); - print_debug("\r\n"); + print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 7e97a27e53..846091a969 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); - print_debug("\r\n"); + print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ @@ -220,7 +220,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("begin msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } enable_fid_change(); @@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("end msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } #endif @@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */ if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 350980e5d2..ecc95d5d67 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -204,7 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_coherent_ht_domain(); @@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 24a307eff6..9e6f973c93 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= mcp55_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index f6d2e54dc6..0174b7b567 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 0935df23ad..cad5252c77 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -82,7 +82,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index cf4501f460..3176c38e22 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -215,7 +215,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -241,7 +241,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -266,7 +266,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c index b13700da44..1503baa6ba 100644 --- a/src/mainboard/olpc/btest/romstage.c +++ b/src/mainboard/olpc/btest/romstage.c @@ -90,7 +90,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) print_debug("computed msr.hi "); print_debug_hex32(msr.hi); - print_debug("\r\n"); + print_debug("\n"); /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ /* well, it may be close. It's about 200,000 ticks */ diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c index b13700da44..1503baa6ba 100644 --- a/src/mainboard/olpc/rev_a/romstage.c +++ b/src/mainboard/olpc/rev_a/romstage.c @@ -90,7 +90,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) print_debug("computed msr.hi "); print_debug_hex32(msr.hi); - print_debug("\r\n"); + print_debug("\n"); /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ /* well, it may be close. It's about 200,000 ticks */ diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 07f11ff647..236e530258 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -98,7 +98,7 @@ static u8 spd_read_byte(u8 device, u8 address) print_debug_hex8(address); print_debug(" returns "); print_debug_hex8(spdbytes[address]); - print_debug("\r\n"); + print_debug("\n"); return spdbytes[address]; } diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 84e29b8e9f..c76f802f58 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 05c62c3e2c..60dd1b275e 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -86,7 +86,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 2edf58c39d..7f668f4c15 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -94,7 +94,7 @@ static void dump_smbus_registers(void) { u32 device; - print_debug("\r\n"); + print_debug("\n"); for (device = 1; device < 0x80; device++) { int j; if (smbus_read_byte(device, 0) < 0) @@ -108,12 +108,12 @@ static void dump_smbus_registers(void) break; } if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\r\n"); + print_debug("\n"); } } @@ -137,13 +137,13 @@ static inline void change_i2c_mux(unsigned device) smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); dump_smbus_registers(); ret = smbus_send_byte(SMBUS_SWITCH1, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); ret = smbus_send_byte_one(SMBUS_SWITCH2, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); } */ @@ -273,7 +273,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); - print_debug("\r\n"); + print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -303,7 +303,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("begin msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } @@ -320,7 +320,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("end msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } #endif @@ -332,7 +332,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 05c62c3e2c..60dd1b275e 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -86,7 +86,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index a56f799c7a..7245b37fb2 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -254,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index 5546421156..b4f2a185b3 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 465ba4c7b3..2531bc2969 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -37,6 +37,6 @@ static void disable_esb6300_watchdog(void) static void disable_watchdogs(void) { disable_esb6300_watchdog(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index 5546421156..b4f2a185b3 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 3904a7dc94..17ec9621ad 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -94,6 +94,6 @@ static void disable_watchdogs(void) // disable_sio_watchdog(NSC_WD_DEV); disable_esb6300_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index 5546421156..b4f2a185b3 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 3904a7dc94..17ec9621ad 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -94,6 +94,6 @@ static void disable_watchdogs(void) // disable_sio_watchdog(NSC_WD_DEV); disable_esb6300_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index 5546421156..b4f2a185b3 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index e9012a49f3..a4c1eec04f 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -94,6 +94,6 @@ static void disable_watchdogs(void) // disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index 5546421156..b4f2a185b3 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -12,7 +12,7 @@ static void print_reg(unsigned char index) print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ static void siodump(void) int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ static void siodump(void) print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ static void dump_bar14(unsigned dev) int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ static void dump_bar14(unsigned dev) val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ void dump_spd_registers(void) while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ void dump_spd_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ void dump_ipmi_registers(void) while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ void dump_ipmi_registers(void) if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index e9012a49f3..a4c1eec04f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -94,6 +94,6 @@ static void disable_watchdogs(void) // disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 4f4cb1505f..f3d6be0a1f 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 1fba17f88b..a16bf7ca51 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 7fd5423c5d..d585edd476 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -56,18 +56,18 @@ static void identify_ts9500(void) TS9500_LED_ON; - print_err("TS-9500 add-on found:\r\n"); + print_err("TS-9500 add-on found:\n"); val=inb(0x19b); for (i=0; i<8; i++) { print_err(" DIP"); print_err_char(i+0x31); print_err(": "); if((val&(1<<i))!=0) - print_err("on\r\n"); + print_err("on\n"); else - print_err("off\r\n"); + print_err("off\n"); } - print_err("\r\n"); + print_err("\n"); val=inb(0x19a); @@ -76,11 +76,11 @@ static void identify_ts9500(void) print_err_char(i+0x30-5); print_err(": "); if((val&(1<<i))!=0) - print_err("on\r\n"); + print_err("on\n"); else - print_err("off\r\n"); + print_err("off\n"); } - print_err("\r\n"); + print_err("\n"); TS9500_LED_OFF; } @@ -92,29 +92,29 @@ static void identify_system(void) print_err("Mainboard: "); val=inb(0x74); switch(val) { - case 0x50: print_err("TS-5300\r\n"); break; - case 0x40: print_err("TS-5400\r\n"); break; - case 0x60: print_err("TS-5500\r\n"); break; - case 0x20: print_err("TS-5600\r\n"); break; - case 0x70: print_err("TS-5700\r\n"); break; - default: print_err("unknown\r\n"); break; + case 0x50: print_err("TS-5300\n"); break; + case 0x40: print_err("TS-5400\n"); break; + case 0x60: print_err("TS-5500\n"); break; + case 0x20: print_err("TS-5600\n"); break; + case 0x70: print_err("TS-5700\n"); break; + default: print_err("unknown\n"); break; } val=inb(0x75); print_err(" SRAM option: "); if((val&1)==0) print_err("not "); - print_err("installed\r\n"); + print_err("installed\n"); print_err(" RS-485 option: "); if((val&2)==0) print_err("not "); - print_err("installed\r\n"); + print_err("installed\n"); val=inb(0x76); print_err(" Temp. range: "); - if((val&2)==0) print_err("commercial\r\n"); - else print_err("industrial\r\n"); + if((val&2)==0) print_err("commercial\n"); + else print_err("industrial\n"); - print_err("\r\n"); + print_err("\n"); val=inb(0x77); for (i=1; i<8; i++) { @@ -122,11 +122,11 @@ static void identify_system(void) print_err_char(i+0x30); print_err(": "); if((val&(1<<i))!=0) - print_err("on\r\n"); + print_err("on\n"); else - print_err("off\r\n"); + print_err("off\n"); } - print_err("\r\n"); + print_err("\n"); /* Detect TS-9500 */ val=inb(0x19d); @@ -157,9 +157,9 @@ static void main(unsigned long bist) console_init(); - print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\r\n"); + print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n"); staticmem(); - print_err("Memory initialized: 32MB\r\n"); + print_err("Memory initialized: 32MB\n"); #if 1 identify_system(); @@ -167,7 +167,7 @@ static void main(unsigned long bist) #if 0 // Check 32MB of memory @ 0 (very slow!) - print_err("Checking memory:\r\n"); + print_err("Checking memory:\n"); ram_check(0x00000000, 0x000a0000); ram_check(0x000b0000, 0x02000000); #endif diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 74d043b04a..b9a566ef11 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -129,9 +129,9 @@ void amd64_main(unsigned long bist) : "=a" (v_esp) ); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); + printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); #else - print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); + print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n"); #endif } @@ -141,9 +141,9 @@ void amd64_main(unsigned long bist) cpu_reset_x: #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset); + printk(BIOS_DEBUG, "cpu_reset = %08x\n",cpu_reset); #else - print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); + print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n"); #endif if(cpu_reset == 0) { @@ -184,21 +184,21 @@ cpu_reset_x: /* We can not go back any more, we lost old stack data in cache as ram*/ if(new_cpu_reset==0) { - print_debug("Use Ram as Stack now - done\r\n"); + print_debug("Use Ram as Stack now - done\n"); } else { - print_debug("Use Ram as Stack now - \r\n"); + print_debug("Use Ram as Stack now - \n"); } #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); + printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); #else - print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); + print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n"); #endif #ifdef DEACTIVATE_CAR print_debug("Deactivating CAR"); #include DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); + print_debug(" - Done.\n"); #endif /*copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); @@ -206,7 +206,7 @@ cpu_reset_x: } #endif - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 3dfc851460..c251e6dcec 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index ee5c659ad8..348083b67b 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 13e5305eea..9d092d8050 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 50593b83bf..bb13bb4246 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 41da91c842..db1342f797 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 470b3e384a..0f1b09e20b 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 149c0c84fb..022fa7ecb0 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ck804_early_setup_x(); if (needs_reset) { - printk(BIOS_INFO, "ht reset -\r\n"); + printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 7c9b43862c..a477b6891d 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -79,7 +79,7 @@ void hardwaremain(int ret_addr) id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 0a07dfede8..85b5321ac8 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -211,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -237,7 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -251,7 +251,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -262,7 +262,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 430e547164..229db170dc 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -66,11 +66,11 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 11c36cb698..d44203c090 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -70,14 +70,14 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); } while ((ret!=0) && (i-->0)); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 960a738b6d..c68c753dad 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -98,26 +98,26 @@ static void main(unsigned long bist) uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); /* ram_check(0, 640 * 1024); */ - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 2d741a1246..0a5ddbc8ae 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -102,7 +102,7 @@ static void main(unsigned long bist) enable_smbus(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -111,10 +111,10 @@ static void main(unsigned long bist) outb(5, 0x80); - print_debug(" Enabling mainboard devices\r\n"); + print_debug(" Enabling mainboard devices\n"); enable_mainboard_devices(); - print_debug(" Enabling shadow ram\r\n"); + print_debug(" Enabling shadow ram\n"); enable_shadow_ram(); ddr_ram_setup((const struct mem_controller *)0); @@ -141,12 +141,12 @@ static void main(unsigned long bist) #endif if (bist == 0) { - print_debug(" Doing MTRR init.\r\n"); + print_debug(" Doing MTRR init.\n"); early_mtrr_init(); } //dump_pci_devices(); - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 80de0afc71..316c0be8c1 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -76,13 +76,13 @@ int acpi_is_wakeup_early_via_vx800(void) device_t dev; u16 tmp, result; - print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); + print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); @@ -94,7 +94,7 @@ int acpi_is_wakeup_early_via_vx800(void) result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; print_debug(" boot_mode="); print_debug_hex16(result); - print_debug("\r\n"); + print_debug("\n"); return result; } @@ -142,7 +142,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x5b, 0x01); #endif - print_debug("In enable_mainboard_devices \r\n"); + print_debug("In enable_mainboard_devices \n"); /* Enable P2P Bridge Header for external PCI bus. */ dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); @@ -482,7 +482,7 @@ void amd64_main(unsigned long bist) * early_mtrr_init() call. */ #if 0 - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); #endif } @@ -490,7 +490,7 @@ void amd64_main(unsigned long bist) /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); /* @@ -501,7 +501,7 @@ void amd64_main(unsigned long bist) Data = pci_read_config8(device, 0xf6); print_debug("NB chip revision ="); print_debug_hex8(Data); - print_debug("\r\n"); + print_debug("\n"); /* Make NB ready before DRAM init. */ via_pci_inittable(Data, mNbStage1InitTbl); @@ -518,7 +518,7 @@ void amd64_main(unsigned long bist) u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; DRAM_SYS_ATTR DramAttr; - print_debug("This is an S3 wakeup\r\n"); + print_debug("This is an S3 wakeup\n"); memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); /* @@ -553,7 +553,7 @@ void amd64_main(unsigned long bist) /* Just copy this function from draminit to here! */ SetUMARam(); - print_debug("Resume from S3, RAM init was ignored\r\n"); + print_debug("Resume from S3, RAM init was ignored\n"); } else { ddr2_ram_setup(); ram_check(0, 640 * 1024); @@ -675,7 +675,7 @@ void amd64_main(unsigned long bist) ); #endif /* This can have function call, because no variable used before this. */ - print_debug("Copy memory to high memory to protect s3 wakeup vector code \r\n"); + print_debug("Copy memory to high memory to protect s3 wakeup vector code \n"); memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), (unsigned char *)0, 0xa0000); memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - @@ -725,11 +725,11 @@ void amd64_main(unsigned long bist) unsigned v_esp; __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); + printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); #else print_debug("v_esp="); print_debug_hex32(v_esp); - print_debug("\r\n"); + print_debug("\n"); #endif } #endif @@ -744,11 +744,11 @@ cpu_reset_x: cpu_reset = 0; #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); + printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); #else print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif if (cpu_reset == 0) @@ -789,16 +789,16 @@ cpu_reset_x: /* We can't go back anymore, we lost old stack data in CAR. */ if (new_cpu_reset == 0) - print_debug("Use Ram as Stack now - done\r\n"); + print_debug("Use Ram as Stack now - done\n"); else - print_debug("Use Ram as Stack now - \r\n"); + print_debug("Use Ram as Stack now - \n"); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); + printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif jason_tsc_count_car(); @@ -808,6 +808,6 @@ cpu_reset_x: } #endif - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 9819048a25..9abef9b962 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -124,7 +124,7 @@ static void main(unsigned long bist) uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); @@ -132,25 +132,25 @@ static void main(unsigned long bist) /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); - print_debug("Enable F-ROM Shadow RAM\r\n"); + print_debug("Enable F-ROM Shadow RAM\n"); enable_shadow_ram(); /* setup cpu */ - print_debug("Setup CPU Interface\r\n"); + print_debug("Setup CPU Interface\n"); c3_cpu_setup(ctrl.d0f2); ddr_ram_setup(); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } //ram_check(0, 640 * 1024); - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/via/vt8454c/debug.c b/src/mainboard/via/vt8454c/debug.c index 54d8cf34e5..3212495f71 100644 --- a/src/mainboard/via/vt8454c/debug.c +++ b/src/mainboard/via/vt8454c/debug.c @@ -42,7 +42,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -50,7 +50,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for (i = 0; i <= 255; i++) { unsigned char val; @@ -62,7 +62,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -90,7 +90,7 @@ static void dump_io_resources(unsigned port) int i; udelay(2000); print_debug_hex16(port); - print_debug(":\r\n"); + print_debug(":\n"); for (i = 0; i < 256; i++) { u8 val; if ((i & 0x0f) == 0) { @@ -101,7 +101,7 @@ static void dump_io_resources(unsigned port) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } port++; } diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 719a3581e6..0680fe1b2a 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -121,7 +121,7 @@ static void main(unsigned long bist) #ifdef DEACTIVATE_CAR print_debug("Deactivating CAR"); #include DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); + print_debug(" - Done.\n"); #endif copy_and_run(0); } diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h index ea4e8947f8..8b1b0a0af1 100644 --- a/src/northbridge/amd/amdk8/amdk8_f.h +++ b/src/northbridge/amd/amdk8/amdk8_f.h @@ -559,7 +559,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) for(i=0; i<sysinfo->nodes; i++) { #ifdef __PRE_RAM__ - print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); + print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif @@ -576,7 +576,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } if(needs_reset) { #ifdef __PRE_RAM__ - print_debug("mem trained failed\r\n"); + print_debug("mem trained failed\n"); soft_reset(); #else printk(BIOS_DEBUG, "mem trained failed\n"); diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 66876c2148..39182854eb 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -111,7 +111,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static void disable_probes(void) @@ -149,7 +149,7 @@ static void disable_probes(void) HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -200,7 +200,7 @@ static void enable_routing(u8 node) val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static void fill_row(u8 node, u8 row, u32 value) @@ -250,7 +250,7 @@ static void rename_temp_node(u8 node) val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static int verify_connection(u8 dest) @@ -513,7 +513,7 @@ static void setup_remote_node(u8 node) pci_write_config32(NODE_MP(7), reg, value); } - print_spew("done\r\n"); + print_spew("done\n"); } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/ @@ -652,7 +652,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) static void setup_uniprocessor(void) { - print_spew("Enabling UP settings\r\n"); + print_spew("Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS==1 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; @@ -1478,7 +1478,7 @@ static unsigned setup_smp(void) { unsigned nodes; - print_spew("Enabling SMP settings\r\n"); + print_spew("Enabling SMP settings\n"); nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 @@ -1496,7 +1496,7 @@ static unsigned setup_smp(void) nodes = setup_smp8(); #endif - printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes); + printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes); return nodes; } @@ -1515,14 +1515,14 @@ static unsigned verify_mp_capabilities(unsigned nodes) #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ if(nodes > 2) { - print_err("Going back to DP\r\n"); + print_err("Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ if(nodes >1 ) { - print_err("Going back to UP\r\n"); + print_err("Going back to UP\n"); return 1; } break; @@ -1601,7 +1601,7 @@ static void coherent_ht_finalize(unsigned nodes) * registers on Hammer A0 revision. */ - print_spew("coherent_ht_finalize\r\n"); + print_spew("coherent_ht_finalize\n"); #if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif @@ -1642,7 +1642,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif } - print_spew("done\r\n"); + print_spew("done\n"); } static int apply_cpu_errata_fixes(unsigned nodes) diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 2e68618100..6a85516211 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -26,7 +26,7 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static uint8_t ht_lookup_capability(device_t dev, uint16_t val) @@ -127,7 +127,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) uint32_t id; freq_cap = pci_read_config16(dev, pos); - printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap); + printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ id = pci_read_config32(dev, 0); @@ -157,8 +157,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) #endif } - printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap); - //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n"); + printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); + //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n"); //freq_cap &= 0x3f; return freq_cap; } @@ -220,14 +220,14 @@ static int ht_optimize_link( int needs_reset; /* Set link width and frequency */ - printk(BIOS_SPEW, "entering ht_optimize_link\r\n"); + printk(BIOS_SPEW, "entering ht_optimize_link\n"); /* Initially assume everything is already optimized and I don't need a reset */ needs_reset = 0; /* Get the frequency capabilities */ freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1)); freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2)); - printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2); + printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2); /* Calculate the highest possible frequency */ freq = log2(freq_cap1 & freq_cap2); @@ -236,11 +236,11 @@ static int ht_optimize_link( old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); /* Set the Calculated link frequency */ pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq); @@ -249,45 +249,45 @@ static int ht_optimize_link( /* Get the width capabilities */ width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1)); width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2)); - printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2); + printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2); /* Calculate dev1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev1 input width=0x%x\n", width); /* Calculate dev1's output width */ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; - printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width); /* See if I am changing dev1's width */ old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width); /* Set dev1's widths */ pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width); /* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width); /* See if I am changing dev2's width */ old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width); /* Set dev2's widths */ pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width); @@ -371,7 +371,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of print_err("udev="); print_err_hex32(udev); print_err("\tupos="); print_err_hex32(upos); print_err("\tuoffs="); print_err_hex32(uoffs); - print_err("\tHT link capability not found\r\n"); + print_err("\tHT link capability not found\n"); break; } @@ -852,16 +852,16 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) unsigned link_pair_num = sysinfo->link_pair_num; - printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n"); - printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num); + printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); + printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); for(i=0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); - printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed); + printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); } reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); - printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed); + printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed); return reset_needed; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5500ce65a7..3d853378d8 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1224,7 +1224,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) e0_later_single_core = 0; } if(e0_later_single_core) { - printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); + printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n"); j=1; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 55cdcaf703..4e402e6d7a 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -25,7 +25,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s%x\r\n", str, val); + printk(BIOS_DEBUG, "%s%x\n", str, val); } #endif } @@ -34,7 +34,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2); + printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); } #endif } @@ -43,14 +43,14 @@ static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } @@ -583,7 +583,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st } } - print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); + print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); print_debug_addr("TrainRcvEn: buf_a:", buf_a); @@ -1401,7 +1401,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in } - print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); + print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a); @@ -1525,25 +1525,25 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); if(TrainRcvrEn(ctrl, Pass, sysinfo)) { return 1; } - print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); return 0; } static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); + printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id); return 1; } else { SetEccDQSRdWrPos(ctrl, sysinfo); } - print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); return 0; } @@ -1700,7 +1700,7 @@ static unsigned int range_to_mtrr(unsigned int reg, } sizek = 1 << align; #if CONFIG_MEM_TRAIN_SEQ != 1 - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\r\n", + printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") @@ -1952,7 +1952,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); } tsc[1] = rdtsc(); @@ -1970,7 +1970,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); } tsc[3] = rdtsc(); @@ -1983,7 +1983,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; dqs_save_MC_NVRAM((ctrl+i)->f2); } @@ -2033,7 +2033,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[1] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i); } @@ -2044,7 +2044,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[2] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); @@ -2055,7 +2055,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[3] = rdtsc(); } diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 329c1afb83..5700c522a2 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -394,7 +394,7 @@ static void test1(void) #if 0 print_debug("spd_count: "); print_debug_hex32(spd_count); - print_debug("\r\n"); + print_debug("\n"); #endif } @@ -410,9 +410,9 @@ static void do_test2(int i) reset_tests(); spd_fail_count = i; - print_debug("\r\nSPD will fail after: "); + print_debug("\nSPD will fail after: "); print_debug_hex32(spd_fail_count); - print_debug(" accesses.\r\n"); + print_debug(" accesses.\n"); memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index cd7b3b54b4..ec3c0cf919 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -5,14 +5,14 @@ static void setup_resource_map_offset(const unsigned int *register_values, int m int i; // print_debug("setting up resource map offset...."); #if 0 - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg; #if 0 - prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]); + prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]); #endif dev = (register_values[i] & ~0xfff) + offset_pci_dev; where = register_values[i] & 0xfff; @@ -27,7 +27,7 @@ static void setup_resource_map_offset(const unsigned int *register_values, int m pci_write_config32(register_values[i], reg); #endif } -// print_debug("done.\r\n"); +// print_debug("done.\n"); } #define RES_PCI_IO 0x10 @@ -45,11 +45,11 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n", + printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i>>2, register_values[i], register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], @@ -112,7 +112,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\n"); #endif } static void setup_resource_map_x(const unsigned int *register_values, int max) @@ -125,11 +125,11 @@ static void setup_resource_map_x(const unsigned int *register_values, int max) #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n", + printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); #endif switch (register_values[i]) { @@ -188,7 +188,7 @@ static void setup_resource_map_x(const unsigned int *register_values, int max) } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\n"); #endif } @@ -223,7 +223,7 @@ static void setup_iob_resource_map(const unsigned int *register_values, int max) print_debug(" -> "); reg = inb(where); print_debug_hex8(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } @@ -262,7 +262,7 @@ static void setup_io_resource_map(const unsigned int *register_values, int max) print_debug(" -> "); reg = inl(where); print_debug_hex32(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } @@ -289,7 +289,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) print_debug(" RB "); reg = read32(where); print_debug_hex32(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c index 02ff7fb599..f61a69b4f8 100644 --- a/src/northbridge/amd/gx1/raminit.c +++ b/src/northbridge/amd/gx1/raminit.c @@ -143,7 +143,7 @@ int comp_banks; #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif /* retrieve the page size from the MC register */ @@ -152,7 +152,7 @@ int comp_banks; #if 0 print_debug(" page_size = "); print_debug_hex32(page_size); - print_debug("\r\n"); + print_debug("\n"); #endif comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12); @@ -169,7 +169,7 @@ int comp_banks; #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift)); } @@ -181,7 +181,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4); @@ -189,7 +189,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ #if 0 print_debug(" page_size = "); print_debug_hex32(page_size); - print_debug("\r\n"); + print_debug("\n"); #endif setGX1Mem(0, TEST_DATA1); @@ -203,7 +203,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)); } @@ -225,7 +225,7 @@ unsigned int probe_config; #if 0 print_debug(" Page size Config = "); print_debug_hex32(page_size_config << dimm_shift); - print_debug("\r\n"); + print_debug("\n"); #endif return(page_size_config << dimm_shift); } @@ -257,7 +257,7 @@ unsigned int test; print_debug("Probing for DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); - print_debug("\r\n"); + print_debug("\n"); setGX1Mem(0, TEST_DATA1); setGX1Mem(0x100, 0); @@ -269,7 +269,7 @@ unsigned int test; print_debug(" Found DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); - print_debug("\r\n"); + print_debug("\n"); return 1; } @@ -285,7 +285,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" Page Size: "); print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4))); - print_debug("\r\n"); + print_debug("\n"); /* Now do component banks detection */ @@ -294,7 +294,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" Component Banks: "); print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30); - print_debug("\r\n"); + print_debug("\n"); /* Now do module banks */ @@ -303,7 +303,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" Module Banks: "); print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30); - print_debug("\r\n"); + print_debug("\n"); mem_config &= (~(DIMM_SZ << dimm_shift)); mem_config |= (size_dimm(dimm_shift)); @@ -311,7 +311,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) print_debug(" DIMM size: "); print_debug_hex32(1 << ((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22); - print_debug("\r\n"); + print_debug("\n"); return (mem_config); } @@ -320,7 +320,7 @@ static void sdram_init(void) { unsigned int mem_config = 0x00700070; - print_debug("Setting up default parameters for memory\r\n"); + print_debug("Setting up default parameters for memory\n"); outb(0x70, 0x80); setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */ @@ -335,7 +335,7 @@ unsigned int mem_config = 0x00700070; enable_dimm(); - print_debug("Sizing memory\r\n"); + print_debug("Sizing memory\n"); setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740); do_refresh(); @@ -346,7 +346,7 @@ unsigned int mem_config = 0x00700070; print_debug("MC_BANK_CFG = "); print_debug_hex32(mem_config); - print_debug("\r\n"); + print_debug("\n"); setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config); enable_dimm(); diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 5e6b68ace6..040d7b7a4e 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -276,11 +276,11 @@ static void pll_reset(void) msr.lo |= PLLMSRlo1; wrmsr(GLCP_SYS_RSTPLL, msr); - print_debug("Reset PLL\n\r"); + print_debug("Reset PLL\n"); msr.lo |= PLLMSRlo2; wrmsr(GLCP_SYS_RSTPLL,msr); - print_debug("should not be here\n\r"); + print_debug("should not be here\n"); #endif print_err("shit"); while (1) @@ -289,7 +289,7 @@ static void pll_reset(void) if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n\r"); + print_debug("reboot from BIOS reset\n"); return; } @@ -310,11 +310,11 @@ static void pll_reset(void) msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24)); wrmsr(0x4c000014, msr); - print_debug("Reset PLL\n\r"); + print_debug("Reset PLL\n"); msr.lo |= ((1<<14) |(1<<13) | (1<<0)); wrmsr(0x4c000014,msr); - print_debug("should not be here\n\r"); + print_debug("should not be here\n"); } #endif // #if USE_GOODRICH_VERSION diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index e45d696e35..b1cb1af6b3 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -21,13 +21,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(0x2000001a); msr.lo = 0x0101; wrmsr(0x2000001a, msr); - //print_debug("sdram_enable step 2\r\n"); + //print_debug("sdram_enable step 2\n"); /* 3. release CKE mask to enable CKE */ msr = rdmsr(0x2000001d); msr.lo &= ~(0x03 << 8); wrmsr(0x2000201d, msr); - //print_debug("sdram_enable step 3\r\n"); + //print_debug("sdram_enable step 3\n"); /* 4. set and clear REF_TST 16 times, more shouldn't hurt * why this is before EMRS and MRS ? */ @@ -38,7 +38,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x01 << 3); wrmsr(0x20000018, msr); } - //print_debug("sdram_enable step 4\r\n"); + //print_debug("sdram_enable step 4\n"); /* 5. set refresh interval */ msr = rdmsr(0x20000018); @@ -50,7 +50,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x03 << 6); msr.lo |= (0x00 << 6); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 5\r\n"); + //print_debug("sdram_enable step 5\n"); /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -58,7 +58,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 28) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 6\r\n"); + //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, * it is documented in LX datasheet */ @@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 27) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 7\r\n"); + //print_debug("sdram_enable step 7\n"); /* 8. load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~0x01; wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 8\r\n"); + //print_debug("sdram_enable step 8\n"); /* wait 200 SDCLKs */ for (i = 0; i < 200; i++) @@ -107,7 +107,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* make sure there is nothing stale in the cache */ __asm__("wbinvd\n"); - print_debug("RAM DLL lock\r\n"); + print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ volatile unsigned long *ptr; for (i=0;i<5;i++) { diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 45a2c9338c..08c19b48e5 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -68,7 +68,7 @@ static void pll_reset(char manualconf) __asm__ __volatile__("hlt\n"); } - print_debug("Done pll_reset\r\n"); + print_debug("Done pll_reset\n"); return; } diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index d22efa61c0..15b5be6ea4 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -32,12 +32,12 @@ static void banner(const char *s) /* This is so ugly. */ print_debug("==========================="); print_debug(s); - print_debug("======================================\r\n"); + print_debug("======================================\n"); } void hcf(void) { - print_emerg("DIE\r\n"); + print_emerg("DIE\n"); /* this guarantees we flush the UART fifos (if any) and also * ensures that things, in general, keep going so no debug output * is lost @@ -200,7 +200,7 @@ static void checkDDRMax(void) /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { - print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n"); + print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); hcf(); } @@ -340,7 +340,7 @@ static void setCAS(void) } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; } else { - print_emerg("DIMM CAS Latencies not compatible\r\n"); + print_emerg("DIMM CAS Latencies not compatible\n"); POST_CODE(ERROR_DIFF_DIMMS); hcf(); } @@ -532,7 +532,7 @@ static void EnableMTest(void) msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(MC_CFCLK_DBUG, msr); - print_info("Enabled MTest for TLA debug\r\n"); + print_info("Enabled MTest for TLA debug\n"); } static void sdram_set_registers(const struct mem_controller *ctrl) @@ -576,7 +576,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) banner("Check DIMM 0"); /* Check DIMM is not Register and not Buffered DIMMs. */ if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_emerg("DIMM0 NOT COMPATIBLE\r\n"); + print_emerg("DIMM0 NOT COMPATIBLE\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); hcf(); } @@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(MC_CF07_DATA); if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { - print_emerg("No memory in the system\r\n"); + print_emerg("No memory in the system\n"); POST_CODE(ERROR_NO_DIMMS); hcf(); } diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index c05059be99..e5d3ac8741 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -27,7 +27,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -40,9 +40,9 @@ static void dump_pci_device(unsigned dev) unsigned char val; if ((i & 0x0f) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x:",i); + printk(BIOS_DEBUG, "\n%02x:",i); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug_char(':'); #endif @@ -55,7 +55,7 @@ static void dump_pci_device(unsigned dev) print_debug_hex8(val); #endif } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -95,7 +95,7 @@ static void dump_pci_devices_on_bus(unsigned busn) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -114,9 +114,9 @@ static void dump_spd_registers(const struct mem_controller *ctrl) unsigned char byte; if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); #endif @@ -133,7 +133,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) print_debug_char(' '); #endif } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -151,9 +151,9 @@ static void dump_spd_registers(const struct mem_controller *ctrl) unsigned char byte; if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); #endif @@ -170,14 +170,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl) print_debug_char(' '); #endif } - print_debug("\r\n"); + print_debug("\n"); } } } static void dump_smbus_registers(void) { unsigned device; - print_debug("\r\n"); + print_debug("\n"); for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; @@ -196,9 +196,9 @@ static void dump_smbus_registers(void) } if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x: ",j); + printk(BIOS_DEBUG, "\n%02x: ",j); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); #endif @@ -211,7 +211,7 @@ static void dump_smbus_registers(void) print_debug_char(' '); #endif } - print_debug("\r\n"); + print_debug("\n"); } } @@ -220,10 +220,10 @@ static void dump_io_resources(unsigned port) int i; #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "%04x:\r\n", port); + printk(BIOS_DEBUG, "%04x:\n", port); #else print_debug_hex16(port); - print_debug(":\r\n"); + print_debug(":\n"); #endif for(i=0;i<256;i++) { uint8_t val; @@ -243,7 +243,7 @@ static void dump_io_resources(unsigned port) print_debug_hex8(val); #endif if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } port++; } @@ -256,9 +256,9 @@ static void dump_mem(unsigned start, unsigned end) for(i=start;i<end;i++) { if((i & 0xf)==0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%08x:", i); + printk(BIOS_DEBUG, "\n%08x:", i); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex32(i); print_debug(":"); #endif @@ -270,6 +270,6 @@ static void dump_mem(unsigned start, unsigned end) print_debug_hex8((unsigned char)*((unsigned char *)i)); #endif } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index c1866070ff..70a692cd92 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -35,7 +35,7 @@ #endif #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) -#define SPD_ERROR "Error reading SPD info\r\n" +#define SPD_ERROR "Error reading SPD info\n" // NOTE: This used to be 0x100000. // That doesn't work on systems where A20M# is asserted, because @@ -481,7 +481,7 @@ static void do_delay(void) static void die_on_spd_error(int spd_return_value) { if (spd_return_value < 0) - die("Error reading SPD info\r\n"); + die("Error reading SPD info\n"); } //---------------------------------------------------------------------------------- @@ -522,7 +522,7 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); if (value < 0) goto hw_err; if (value > 2) - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); if (value == 2) { pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently @@ -755,7 +755,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n"); + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); continue; } @@ -780,11 +780,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i))); } else - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n"); + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); #else switch (bDualChannel) { case 0: - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n"); + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); break; default: @@ -873,7 +873,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); - RAM_DEBUG_MESSAGE("\r\n"); + RAM_DEBUG_MESSAGE("\n"); read32(dimm_start_address + e7501_mode_bits); // Set the start of the next DIMM @@ -1017,10 +1017,10 @@ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl, RAM_DEBUG_HEX32(sz.side1); RAM_DEBUG_MESSAGE(" "); RAM_DEBUG_HEX32(sz.side2); - RAM_DEBUG_MESSAGE("\r\n"); + RAM_DEBUG_MESSAGE("\n"); if (sz.side1 == 0) - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); } @@ -1105,7 +1105,7 @@ static void initialize_ecc(void) uint8_t byte; - RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n"); + RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); /* Initialize ECC bits , use ECC zero mode (new to 7501)*/ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); @@ -1117,7 +1117,7 @@ static void initialize_ecc(void) } while ( (byte & 0x08 ) == 0); pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); - RAM_DEBUG_MESSAGE("ECC state initialized.\r\n"); + RAM_DEBUG_MESSAGE("ECC state initialized.\n"); /* Clear the ECC error bits */ pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); @@ -1373,7 +1373,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8 } } else - die("No CAS# latencies compatible with all DIMMs!!\r\n"); + die("No CAS# latencies compatible with all DIMMs!!\n"); pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); @@ -1462,14 +1462,14 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct die_on_spd_error(value); value &= 0x7f; // Mask off self-refresh bit if(value > MAX_SPD_REFRESH_RATE) { - print_err("unsupported refresh rate\r\n"); + print_err("unsupported refresh rate\n"); continue; } // Get the appropriate E7501 refresh mode for this DIMM dimm_refresh_mode = refresh_rate_map[value]; if (dimm_refresh_mode > 7) { - print_err("unsupported refresh rate\r\n"); + print_err("unsupported refresh rate\n"); continue; } @@ -1680,7 +1680,7 @@ static void ram_set_rcomp_regs(void) uint32_t dword; uint8_t maybe_strength_control; - RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n"); + RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); /*enable access to the rcomp bar*/ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); @@ -1805,8 +1805,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) return; /* 1 & 2 Power up and start clocks */ - RAM_DEBUG_MESSAGE("Ram Enable 1\r\n"); - RAM_DEBUG_MESSAGE("Ram Enable 2\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 1\n"); + RAM_DEBUG_MESSAGE("Ram Enable 2\n"); /* A 200us delay is needed */ @@ -1814,23 +1814,23 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) EXTRA_DELAY /* 3. Apply NOP */ - RAM_DEBUG_MESSAGE("Ram Enable 3\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); EXTRA_DELAY /* 4 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 4\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); EXTRA_DELAY /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 5\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 5\n"); do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); EXTRA_DELAY /* 6. Reset DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 6\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 6\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); EXTRA_DELAY @@ -1842,12 +1842,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) EXTRA_DELAY /* 7 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 7\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); EXTRA_DELAY /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 8\n"); do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY do_ram_command(RAM_COMMAND_CBR, 0); @@ -1867,17 +1867,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) EXTRA_DELAY /* 9 mode register set */ - RAM_DEBUG_MESSAGE("Ram Enable 9\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); EXTRA_DELAY /* 10 DDR Receive FIFO RE-Sync */ - RAM_DEBUG_MESSAGE("Ram Enable 10\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 10\n"); RAM_RESET_DDR_PTR(); EXTRA_DELAY /* 11 normal operation */ - RAM_DEBUG_MESSAGE("Ram Enable 11\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); EXTRA_DELAY @@ -1897,7 +1897,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n"); + RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); DUMPNORTH(); // verify_ram(); @@ -1917,19 +1917,19 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { uint8_t dimm_mask; - RAM_DEBUG_MESSAGE("Reading SPD data...\r\n"); + RAM_DEBUG_MESSAGE("Reading SPD data...\n"); //activate_spd_rom(ctrl); Not necessary for this chipset dimm_mask = spd_get_supported_dimms(ctrl); if (dimm_mask == 0) { - print_debug("No usable memory for this controller\r\n"); + print_debug("No usable memory for this controller\n"); } else { enable_e7501_clocks(dimm_mask); - RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n"); + RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); configure_e7501_row_attributes(ctrl, dimm_mask); configure_e7501_dram_controller_mode(ctrl, dimm_mask); @@ -1938,7 +1938,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) configure_e7501_dram_timing(ctrl, dimm_mask); DO_DELAY - RAM_DEBUG_MESSAGE("done\r\n"); + RAM_DEBUG_MESSAGE("done\n"); } // NOTE: configure_e7501_ram_addresses() is NOT called here. @@ -1963,7 +1963,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) // static void sdram_set_registers(const struct mem_controller *ctrl) { - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n"); + RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); ram_set_rcomp_regs(); diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c index 3b9b696a21..133d1c4f88 100644 --- a/src/northbridge/intel/e7520/memory_initialized.c +++ b/src/northbridge/intel/e7520/memory_initialized.c @@ -7,7 +7,7 @@ static inline int memory_initialized(void) drc = pci_read_config32(NB_DEV, DRC); //print_debug("memory_initialized: DRC: "); //print_debug_hex32(drc); - //print_debug("\r\n"); + //print_debug("\n"); return (drc & (1<<29)); } diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 3965addcb2..836e6f8c7c 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -74,7 +74,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -155,7 +155,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -283,7 +283,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; @@ -538,7 +538,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -576,7 +576,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, ecc = 2; } else if (ecc == 1) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else if ( reg == 7 ) { @@ -584,15 +584,15 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, ecc = 1; } else if ( ecc > 1 ) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else { - die("ERROR - RAM not DDR\r\n"); + die("ERROR - RAM not DDR\n"); } } else { - die("ERROR - Non ECC memory dimm\r\n"); + die("ERROR - Non ECC memory dimm\n"); } value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ @@ -621,10 +621,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, ecc = 2; if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ - print_debug("ECC off\r\n"); + print_debug("ECC off\n"); } else { - print_debug("ECC on\r\n"); + print_debug("ECC on\n"); } drc &= ~(3 << 20); /* clear the ecc bits */ drc |= (ecc << 20); /* or in the calculated ecc bits */ @@ -654,7 +654,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -669,7 +669,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -771,12 +771,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32); @@ -1009,7 +1009,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(BAR+DCALDATA+(16*4), 0x00000000); @@ -1075,7 +1075,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ #ifdef DIMM_MAP_LOGICAL @@ -1087,7 +1087,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } pll_setup(drc); data32 = drc & ~(3 << 20); /* clear ECC mode */ @@ -1124,7 +1124,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); @@ -1307,7 +1307,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } @@ -1324,13 +1324,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 |= (1 << 31); pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 4aaa26480d..0d18022020 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -74,7 +74,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -155,7 +155,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -283,7 +283,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; @@ -538,7 +538,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -576,7 +576,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, ecc = 2; } else if (ecc == 1) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else if ( reg == 7 ) { @@ -584,15 +584,15 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, ecc = 1; } else if ( ecc > 1 ) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else { - die("ERROR - RAM not DDR\r\n"); + die("ERROR - RAM not DDR\n"); } } else { - die("ERROR - Non ECC memory dimm\r\n"); + die("ERROR - Non ECC memory dimm\n"); } value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ @@ -621,10 +621,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, ecc = 2; if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ - print_debug("ECC off\r\n"); + print_debug("ECC off\n"); } else { - print_debug("ECC on\r\n"); + print_debug("ECC on\n"); } drc &= ~(3 << 20); /* clear the ecc bits */ drc |= (ecc << 20); /* or in the calculated ecc bits */ @@ -654,7 +654,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -669,7 +669,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -742,12 +742,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, 0xb0, data32); @@ -980,7 +980,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(BAR+DCALDATA+(16*4), 0x00000000); @@ -1046,7 +1046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ #ifdef DIMM_MAP_LOGICAL @@ -1058,7 +1058,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 & ~(7 << 8); /* clear refresh rates */ @@ -1094,7 +1094,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); @@ -1274,7 +1274,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } @@ -1291,13 +1291,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 |= (1 << 31); pci_write_config32(ctrl->f0, 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(ctrl->f0, 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 76475ce235..fa44d599f1 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -76,7 +76,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } struct dimm_size { @@ -149,7 +149,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -277,7 +277,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; @@ -528,7 +528,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -556,7 +556,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, continue; } value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */ - if (value != 2) die("ERROR - Non ECC memory dimm\r\n"); + if (value != 2) die("ERROR - Non ECC memory dimm\n"); value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ value &= 0x0f; /* clip self refresh bit */ @@ -595,7 +595,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -683,12 +683,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DDR2ODTC, data32); @@ -921,7 +921,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(MCBAR+DCALDATA+(16*4), 0x00000000); @@ -977,7 +977,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ #ifdef DIMM_MAP_LOGICAL @@ -989,7 +989,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 & ~(7 << 8); /* clear refresh rates */ @@ -1024,7 +1024,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<8;i+=2) { /* loop through each dimm to test */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); @@ -1177,7 +1177,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(MCBAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(MCBAR+DCALDATA+i, 0x00000000); } @@ -1194,13 +1194,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 |= (1 << 31); pci_write_config32(ctrl->f0, 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(ctrl->f0, 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 9ad778bf13..5a4a328e44 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -134,7 +134,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) print_debug_hex8(sz.side1); print_debug("."); print_debug_hex8(sz.side2); - print_debug("\r\n"); + print_debug("\n"); return sz; } @@ -167,14 +167,14 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) } print_debug("DRB = "); print_debug_hex32(pci_read_config32(ctrl->f0, DRB)); - print_debug("\r\n"); + print_debug("\n"); cum >>= 1; /* set TOM top of memory */ pci_write_config16(ctrl->f0, TOM, cum); print_debug("TOM = "); print_debug_hex16(cum); - print_debug("\r\n"); + print_debug("\n"); /* set TOLM top of low memory */ if (cum > 0x18) { cum = 0x18; @@ -183,7 +183,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) pci_write_config16(ctrl->f0, TOLM, cum); print_debug("TOLM = "); print_debug_hex16(cum); - print_debug("\r\n"); + print_debug("\n"); return 0; } @@ -202,7 +202,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl) print_debug_hex8(device); print_debug(" = "); print_debug_hex8(byte); - print_debug("\r\n"); + print_debug("\n"); if (byte == 8) { dimm_mask |= (1 << i); } @@ -227,29 +227,29 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, } value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS); - if (value < 0) die("Bad SPD data\r\n"); - if ((value & 0xf) == 0) die("Invalid # of rows\r\n"); + if (value < 0) die("Bad SPD data\n"); + if ((value & 0xf) == 0) die("Invalid # of rows\n"); dra |= (((value-13) & 0x7) << 23); dra |= (((value-13) & 0x7) << 29); reg += value & 0xf; value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS); - if (value < 0) die("Bad SPD data\r\n"); - if ((value & 0xf) == 0) die("Invalid # of columns\r\n"); + if (value < 0) die("Bad SPD data\n"); + if ((value & 0xf) == 0) die("Invalid # of columns\n"); dra |= (((value-10) & 0x7) << 20); dra |= (((value-10) & 0x7) << 26); reg += value & 0xf; value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM); - if (value < 0) die("Bad SPD data\r\n"); - if ((value & 0xff) == 0) die("Invalid # of banks\r\n"); + if (value < 0) die("Bad SPD data\n"); + if ((value & 0xff) == 0) die("Invalid # of banks\n"); reg += log2(value & 0xff); print_debug("dimm "); print_debug_hex8(i); print_debug(" reg = "); print_debug_hex8(reg); - print_debug("\r\n"); + print_debug("\n"); /* set device density */ dra |= ((31-reg)); @@ -270,7 +270,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, print_debug_hex8(i); print_debug(" = "); print_debug_hex32(dra); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DRA + (i*4), dra); } @@ -320,10 +320,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, else if (val & 0x40) cl = 6; else - die("CAS latency mismatch\r\n"); + die("CAS latency mismatch\n"); print_debug("cl = "); print_debug_hex8(cl); - print_debug("\r\n"); + print_debug("\n"); ci = cycle[index]; @@ -349,10 +349,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, } print_debug("trc = "); print_debug_hex8(trc); - print_debug("\r\n"); + print_debug("\n"); print_debug("trfc = "); print_debug_hex8(trfc); - print_debug("\r\n"); + print_debug("\n"); /* Tras, Trtp, Twtr in cycles */ for (i = 0; i < DIMM_SOCKETS; i++) { @@ -374,38 +374,38 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, } print_debug("tras = "); print_debug_hex8(tras); - print_debug("\r\n"); + print_debug("\n"); print_debug("trtp = "); print_debug_hex8(trtp); - print_debug("\r\n"); + print_debug("\n"); print_debug("twtr = "); print_debug_hex8(twtr); - print_debug("\r\n"); + print_debug("\n"); val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9) | ((cl - 3) << 6) | ((cl - 3) << 3)); print_debug("drt0 = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DRT0, val); val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25) | (twtr << 15)); print_debug("drt1 = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DRT1, val); val = (magic[index]); print_debug("magic = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val); val = (mrs[index] | (cl << 20)); print_debug("mrs = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); return val; } @@ -422,11 +422,11 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, if (!(dimm_mask & (1 << i))) continue; if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40) - die("ERROR: Only 64-bit DIMMs supported\r\n"); + die("ERROR: Only 64-bit DIMMs supported\n"); if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02)) - die("ERROR: Only ECC DIMMs supported\r\n"); + die("ERROR: Only ECC DIMMs supported\n"); if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08) - die("ERROR: Only x8 DIMMs supported\r\n"); + die("ERROR: Only x8 DIMMs supported\n"); value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if (value > cycle) @@ -434,7 +434,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, } print_debug("cycle = "); print_debug_hex8(cycle); - print_debug("\r\n"); + print_debug("\n"); drc |= (1 << 20); /* enable ECC */ drc |= (3 << 30); /* enable CKE on each DIMM */ @@ -446,42 +446,42 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, print_debug("msr 0xcd = "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); /* TODO check that this msr really indicates fsb speed! */ if (msr.lo & 0x07) { - print_info("533 MHz FSB\r\n"); + print_info("533 MHz FSB\n"); if (cycle <= 0x25) { drc |= 0x5; - print_info("400 MHz DDR\r\n"); + print_info("400 MHz DDR\n"); } else if (cycle <= 0x30) { drc |= 0x7; - print_info("333 MHz DDR\r\n"); + print_info("333 MHz DDR\n"); } else if (cycle <= 0x3d) { drc |= 0x4; - print_info("266 MHz DDR\r\n"); + print_info("266 MHz DDR\n"); } else { drc |= 0x2; - print_info("200 MHz DDR\r\n"); + print_info("200 MHz DDR\n"); } } else { - print_info("400 MHz FSB\r\n"); + print_info("400 MHz FSB\n"); if (cycle <= 0x30) { drc |= 0x7; - print_info("333 MHz DDR\r\n"); + print_info("333 MHz DDR\n"); } else if (cycle <= 0x3d) { drc |= 0x0; - print_info("266 MHz DDR\r\n"); + print_info("266 MHz DDR\n"); } else { drc |= 0x2; - print_info("200 MHz DDR\r\n"); + print_info("200 MHz DDR\n"); } } print_debug("DRC = "); print_debug_hex32(drc); - print_debug("\r\n"); + print_debug("\n"); return drc; } @@ -494,7 +494,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* Test if we can read the SPD */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -524,14 +524,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DDR2ODTC, data32); for (i = 0; i < 2; i++) { print_debug("ODT CS"); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21)); @@ -547,14 +547,14 @@ static void dump_dcal_regs(void) int i; for (i = 0x0; i < 0x2a0; i += 4) { if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug(": "); } print_debug_hex32(read32(BAR+i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } @@ -570,12 +570,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) u16 data16; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* Set DRAM type and Front Side Bus frequency */ drc = spd_set_dram_controller_mode(ctrl, mask); if (drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 | (3 << 5); /* temp turn off ODT */ @@ -600,7 +600,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); udelay(16); write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21))); write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21))); @@ -614,7 +614,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) @@ -626,7 +626,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -639,7 +639,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -651,7 +651,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -664,7 +664,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -678,7 +678,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("Refresh CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) @@ -691,7 +691,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -704,7 +704,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -728,7 +728,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for (cs = 0; cs < 1; cs++) { print_debug("receive enable calibration CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) @@ -755,17 +755,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) continue; print_debug("clear memory CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16)); data32 = read32(BAR+MBCSR); while (data32 & 0x80000000) data32 = read32(BAR+MBCSR); if (data32 & 0x40000000) - print_debug("failed!\r\n"); + print_debug("failed!\n"); } /* Clear read/write FIFO pointers */ - print_debug("clear read/write fifo pointers\r\n"); + print_debug("clear read/write fifo pointers\n"); write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15)); udelay(16); write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15)); @@ -773,7 +773,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dump_dcal_regs(); - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ drc |= (1 << 29); diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index fab224dc85..b437755213 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -2,7 +2,7 @@ static void dump_spd_registers(void) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM_SPD_BASE + i; @@ -16,20 +16,20 @@ static void dump_spd_registers(void) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 016bf67f93..789ea82db9 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -420,7 +420,7 @@ static void do_ram_command(u32 command) PRINT_DEBUG_HEX16(reg16); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); @@ -606,7 +606,7 @@ static void spd_enable_refresh(void) PRINT_DEBUG_HEX8(reg); PRINT_DEBUG(") for DIMM "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } pci_write_config8(NB, DRAMC, reg); @@ -621,7 +621,7 @@ static void sdram_set_registers(void) int i, max; uint8_t reg; - PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); max = ARRAY_SIZE(register_values); @@ -637,7 +637,7 @@ static void sdram_set_registers(void) PRINT_DEBUG_HEX8(register_values[i]); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif } } @@ -731,11 +731,11 @@ static void set_dram_row_attributes(void) } PRINT_DEBUG("DIMM in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); if (edosd == 0x06) { - print_err("Mixing EDO/SDRAM unsupported!\r\n"); - die("HALT\r\n"); + print_err("Mixing EDO/SDRAM unsupported!\n"); + die("HALT\n"); } /* "DRA" is our RPS for the two rows on this DIMM. */ @@ -816,12 +816,12 @@ static void set_dram_row_attributes(void) if (col == 4) bpr |= 0xc0; } else { - print_err("# of banks of DIMM unsupported!\r\n"); - die("HALT\r\n"); + print_err("# of banks of DIMM unsupported!\n"); + die("HALT\n"); } if (dra == -1) { - print_err("Page size not supported\r\n"); - die("HALT\r\n"); + print_err("Page size not supported\n"); + die("HALT\n"); } /* @@ -831,14 +831,14 @@ static void set_dram_row_attributes(void) */ struct dimm_size sz = spd_get_dimm_size(device); if ((sz.side1 < 8)) { - print_err("DIMMs smaller than 8MB per side\r\n" - "are not supported on this NB.\r\n"); - die("HALT\r\n"); + print_err("DIMMs smaller than 8MB per side\n" + "are not supported on this NB.\n"); + die("HALT\n"); } if ((sz.side1 > 128)) { - print_err("DIMMs > 128MB per side\r\n" - "are not supported on this NB\r\n"); - die("HALT\r\n"); + print_err("DIMMs > 128MB per side\n" + "are not supported on this NB\n"); + die("HALT\n"); } /* Divide size by 8 to set up the DRB registers. */ @@ -855,7 +855,7 @@ static void set_dram_row_attributes(void) #if 0 PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif /* If there's no DIMM in the slot, set dra to 0x00. */ @@ -870,7 +870,7 @@ static void set_dram_row_attributes(void) #if 0 PRINT_DEBUG("DRB has been set to 0x"); PRINT_DEBUG_HEX16(drb); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif /* Brings the upper DRB back down to be base for @@ -886,19 +886,19 @@ static void set_dram_row_attributes(void) pci_write_config8(NB, PGPOL + 1, bpr); PRINT_DEBUG("PGPOL[BPR] has been set to 0x"); PRINT_DEBUG_HEX8(bpr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Set DRAM row page size register. */ pci_write_config16(NB, RPS, rps); PRINT_DEBUG("RPS has been set to 0x"); PRINT_DEBUG_HEX16(rps); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* ### ECC */ pci_write_config8(NB, NBXCFG + 3, nbxecc); PRINT_DEBUG("NBXECC[31:24] has been set to 0x"); PRINT_DEBUG_HEX8(nbxecc); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). * TODO: Registered SDRAM support. @@ -917,7 +917,7 @@ static void set_dram_row_attributes(void) pci_write_config8(NB, DRAMC, value); PRINT_DEBUG("DRAMC has been set to 0x"); PRINT_DEBUG_HEX8(value); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } static void sdram_set_spd_registers(void) @@ -947,38 +947,38 @@ static void sdram_enable(void) udelay(200); /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG("RAM Enable 3: CBR\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ - PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG("RAM Enable 5: Normal operation\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */ - PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); + PRINT_DEBUG("RAM Enable 6: Enable refresh\n"); // pci_write_config8(NB, PMCR, 0x10); spd_enable_refresh(); udelay(1); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); } diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index 5d07441dde..6259608b48 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -171,7 +171,7 @@ static void do_ram_command(u32 command) PRINT_DEBUG_HEX16(reg16); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); @@ -201,7 +201,7 @@ static void spd_enable_refresh(void) PRINT_DEBUG("spd_enable_refresh: dramc = 0x"); PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } /*----------------------------------------------------------------------------- @@ -225,7 +225,7 @@ static void northbridge_init(void) reg32 = pci_read_config32(NB, APBASE); PRINT_DEBUG("APBASE "); PRINT_DEBUG_HEX32(reg32); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif } @@ -244,10 +244,10 @@ static void sdram_set_registers(void) #if 0 uint16_t reg16; reg16 = pci_read_config16(NB, PACCFG); - printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6'); + printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6'); #endif - PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); northbridge_init(); @@ -279,11 +279,11 @@ static void sdram_set_registers(void) } else { PRINT_DEBUG(" FAIL "); } - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif } - PRINT_DEBUG("Northbridge atexit sdram set registers\r\n"); + PRINT_DEBUG("Northbridge atexit sdram set registers\n"); DUMPNORTH(); } @@ -342,7 +342,7 @@ static void sdram_set_spd_registers(void) */ PRINT_DEBUG_HEX16(ds); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); memsize += ds; @@ -363,7 +363,7 @@ static void sdram_set_spd_registers(void) PRINT_DEBUG(" "); PRINT_DEBUG_HEX16(ds); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* * modify DRT register if current row isn't empty @@ -384,7 +384,7 @@ static void sdram_set_spd_registers(void) #if 0 PRINT_DEBUG("Mem: 0x"); PRINT_DEBUG_HEX16(memsize * 8); - PRINT_DEBUG(" MB\r\n"); + PRINT_DEBUG(" MB\n"); if (memsize == 0) { /* maybe we should use some nice die/hlt sequence with printing on console @@ -392,8 +392,8 @@ static void sdram_set_spd_registers(void) * maybe such event_handler can be commonly defined routine to decrease * code duplication? */ - PRINT_DEBUG("No memory detected via SPD\r\n"); - PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\r\n"); + PRINT_DEBUG("No memory detected via SPD\n"); + PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\n"); } #endif @@ -418,38 +418,38 @@ static void sdram_enable(void) udelay(200); /* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG("RAM Enable 3: CBR\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ - PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG("RAM Enable 5: Normal operation\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */ - PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); + PRINT_DEBUG("RAM Enable 6: Enable refresh\n"); pci_write_config8(NB, DRAMC, 0x01); spd_enable_refresh(); udelay(1); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); } diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 5733700af3..87b039f5f5 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -2,7 +2,7 @@ static void dump_spd_registers(void) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM_SPD_BASE + i; @@ -16,20 +16,20 @@ static void dump_spd_registers(void) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index e88580c5e8..86602eae34 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -150,7 +150,7 @@ static void do_ram_command(u8 command) PRINT_DEBUG_HEX8(reg8); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); @@ -164,7 +164,7 @@ static void do_ram_command(u8 command) PRINT_DEBUG_HEX8(reg8); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); } @@ -194,14 +194,14 @@ static void spd_set_dram_size(void) if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31); /* WISHLIST: would be nice to display it as decimal? */ print_debug("DIMM is 0x"); print_debug_hex8(dimm_size * 4); - print_debug("MB\r\n"); + print_debug("MB\n"); /* The i810 can't handle DIMMs larger than 128MB per * side. This will fail if the DIMM uses a @@ -211,9 +211,9 @@ static void spd_set_dram_size(void) */ if (dimm_size > 32) { print_err("DIMM row sizes larger than 128MB not" - "supported on i810\r\n"); + "supported on i810\n"); print_err - ("Attempting to treat as 128MB DIMM\r\n"); + ("Attempting to treat as 128MB DIMM\n"); dimm_size = 32; } @@ -225,19 +225,19 @@ static void spd_set_dram_size(void) print_debug("After translation, dimm_size is 0x"); print_debug_hex8(dimm_size); - print_debug("\r\n"); + print_debug("\n"); /* If the DIMM is dual-sided, the DRP value is +2 */ /* TODO: Figure out asymetrical configurations. */ if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) == 0xff) { - print_debug("DIMM is dual-sided\r\n"); + print_debug("DIMM is dual-sided\n"); dimm_size += 2; } } else { print_debug("No DIMM found in slot "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* If there's no DIMM in the slot, set value to 0. */ dimm_size = 0x00; @@ -249,7 +249,7 @@ static void spd_set_dram_size(void) print_debug("DRP calculated to 0x"); print_debug_hex8(drp); - print_debug("\r\n"); + print_debug("\n"); pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp); } @@ -354,7 +354,7 @@ static void set_dram_buffer_strength(void) print_debug("BUFF_SC calculated to 0x"); print_debug_hex16(buff_sc); - print_debug("\r\n"); + print_debug("\n"); pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc); } @@ -411,32 +411,32 @@ static void sdram_enable(void) int i; /* 1. Apply NOP. */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG("RAM Enable 3: CBR\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation (enables refresh at 15.6usec). */ - PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG("RAM Enable 5: Normal operation\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); } diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c index f97eaa893d..c9cbdbb8ec 100644 --- a/src/northbridge/intel/i82830/raminit.c +++ b/src/northbridge/intel/i82830/raminit.c @@ -79,7 +79,7 @@ static void do_ram_command(u32 command) pci_write_config32(NORTHBRIDGE, DRC, reg32); PRINT_DEBUG("RAM command 0x"); PRINT_DEBUG_HEX32(reg32); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } static void ram_read32(u8 dimm_start, u32 offset) @@ -89,24 +89,24 @@ static void ram_read32(u8 dimm_start, u32 offset) PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); PRINT_DEBUG(" => 0x"); PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); PRINT_DEBUG(" Writing RAM at 0x"); PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); PRINT_DEBUG(" <= 0x"); PRINT_DEBUG_HEX32(offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); write32(dimm_start * 32 * 1024 * 1024, offset); PRINT_DEBUG(" Reading RAM at 0x"); PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); PRINT_DEBUG(" => 0x"); PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } else { PRINT_DEBUG(" Sending RAM command to 0x"); PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); read32((dimm_start * 32 * 1024 * 1024) + offset); } } @@ -141,7 +141,7 @@ static void initialize_dimm_rows(void) if (dimm_end > dimm_start) { print_debug("Initializing SDRAM Row "); print_debug_hex8(row); - print_debug("\r\n"); + print_debug("\n"); /* NOP command */ PRINT_DEBUG(" NOP "); @@ -177,7 +177,7 @@ static void initialize_dimm_rows(void) udelay(1); /* Perform a dummy memory read/write cycle */ - PRINT_DEBUG(" Performing dummy read/write\r\n"); + PRINT_DEBUG(" Performing dummy read/write\n"); ram_read32(dimm_start, 0x55aa55aa); udelay(1); } @@ -256,29 +256,29 @@ static void set_dram_row_boundaries(void) if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); sz = spd_get_dimm_size(device); /* WISHLIST: would be nice to display it as decimal? */ print_debug("DIMM is 0x"); print_debug_hex16(sz.side1); - print_debug(" on side 1\r\n"); + print_debug(" on side 1\n"); print_debug("DIMM is 0x"); print_debug_hex16(sz.side2); - print_debug(" on side 2\r\n"); + print_debug(" on side 2\n"); /* - Memory compatibility checks - */ /* Test for PC133 (i82830 only supports PC133) */ /* PC133 SPD9 - cycle time is always 75 */ if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) { - print_err("SPD9 DIMM Is Not PC133 Compatable\r\n"); - die("HALT\r\n"); + print_err("SPD9 DIMM Is Not PC133 Compatable\n"); + die("HALT\n"); } /* PC133 SPD10 - access time is always 54 */ if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) { - print_err("SPD10 DIMM Is Not PC133 Compatable\r\n"); - die("HALT\r\n"); + print_err("SPD10 DIMM Is Not PC133 Compatable\n"); + die("HALT\n"); } /* The i82830 only supports a symmetrical dual-sided dimms @@ -286,23 +286,23 @@ static void set_dram_row_boundaries(void) * side or larger than 256MB per side. */ if ((sz.side2 != 0) && (sz.side1 != sz.side2)) { - print_err("This northbridge only supports\r\n"); - print_err("symmetrical dual-sided DIMMs\r\n"); - print_err("booting as a single-sided DIMM\r\n"); + print_err("This northbridge only supports\n"); + print_err("symmetrical dual-sided DIMMs\n"); + print_err("booting as a single-sided DIMM\n"); sz.side2 = 0; } if ((sz.side1 < 32)) { - print_err("DIMMs smaller than 32MB per side\r\n"); - print_err("are not supported on this northbridge\r\n"); - die("HALT\r\n"); + print_err("DIMMs smaller than 32MB per side\n"); + print_err("are not supported on this northbridge\n"); + die("HALT\n"); } if ((sz.side1 > 256)) { print_err - ("DIMMs larger than 256MB per side\r\n"); + ("DIMMs larger than 256MB per side\n"); print_err - ("are not supported on this northbridge\r\n"); - die("HALT\r\n"); + ("are not supported on this northbridge\n"); + die("HALT\n"); } /* - End Memory compatibility checks - */ @@ -316,7 +316,7 @@ static void set_dram_row_boundaries(void) } else { PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* If there's no DIMM in the slot, set value to 0. */ drb1 = 0; @@ -330,12 +330,12 @@ static void set_dram_row_boundaries(void) PRINT_DEBUG_HEX8(DRB); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(drb1); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); PRINT_DEBUG("DRB1 0x"); PRINT_DEBUG_HEX8(DRB + 1); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(drb1 + drb2); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } else if (i == 1) { value = pci_read_config8(NORTHBRIDGE, DRB + 1); pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1); @@ -344,12 +344,12 @@ static void set_dram_row_boundaries(void) PRINT_DEBUG_HEX8(DRB + 2); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(value + drb1); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); PRINT_DEBUG("DRB3 0x"); PRINT_DEBUG_HEX8(DRB + 3); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(value + drb1 + drb2); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* We need to set the highest DRB value to 0x64 and 0x65. * These are supposed to be "Reserved" but memory will @@ -374,7 +374,7 @@ static void set_dram_row_attributes(void) if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); - print_debug(", setting DRA...\r\n"); + print_debug(", setting DRA...\n"); dra = 0x00; @@ -403,8 +403,8 @@ static void set_dram_row_attributes(void) } else if (dra == 16) { dra = 0xF3; /* 16KB */ } else { - print_err("Page size not supported\r\n"); - die("HALT\r\n"); + print_err("Page size not supported\n"); + die("HALT\n"); } } else if (value == 2) { if (dra == 2) { @@ -416,18 +416,18 @@ static void set_dram_row_attributes(void) } else if (dra == 16) { dra = 0x33; /* 16KB */ } else { - print_err("Page size not supported\r\n"); - die("HALT\r\n"); + print_err("Page size not supported\n"); + die("HALT\n"); } } else { - print_err("# of banks of DIMM not supported\r\n"); - die("HALT\r\n"); + print_err("# of banks of DIMM not supported\n"); + die("HALT\n"); } } else { PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG(", setting DRA to 0xFF\r\n"); + PRINT_DEBUG(", setting DRA to 0xFF\n"); /* If there's no DIMM in the slot, set dra value to 0xFF. */ dra = 0xFF; @@ -439,7 +439,7 @@ static void set_dram_row_attributes(void) PRINT_DEBUG_HEX8(DRA + i); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(dra); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } } @@ -468,7 +468,7 @@ Public interface. static void sdram_set_registers(void) { - PRINT_DEBUG("Setting initial sdram registers....\r\n"); + PRINT_DEBUG("Setting initial sdram registers....\n"); /* Calculate the value for DRT DRAM Timing Register */ set_dram_timing(); @@ -482,7 +482,7 @@ static void sdram_set_registers(void) /* Setup DRAM Row Attribute Registers */ set_dram_row_attributes(); - PRINT_DEBUG("Initial sdram registers have been set.\r\n"); + PRINT_DEBUG("Initial sdram registers have been set.\n"); } static void northbridge_set_registers(void) @@ -490,7 +490,7 @@ static void northbridge_set_registers(void) u16 value; int igd_memory = 0; - PRINT_DEBUG("Setting initial nothbridge registers....\r\n"); + PRINT_DEBUG("Setting initial nothbridge registers....\n"); /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); @@ -536,7 +536,7 @@ static void northbridge_set_registers(void) value |= 1; // 64MB aperture pci_write_config16(NORTHBRIDGE, GCC1, value); - PRINT_DEBUG("Initial northbridge registers have been set.\r\n"); + PRINT_DEBUG("Initial northbridge registers have been set.\n"); } static void sdram_initialize(void) @@ -554,13 +554,13 @@ static void sdram_initialize(void) initialize_dimm_rows(); /* Enable Refresh */ - PRINT_DEBUG("Enabling Refresh\r\n"); + PRINT_DEBUG("Enabling Refresh\n"); reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 |= (RAM_COMMAND_REFRESH << 8); pci_write_config32(NORTHBRIDGE, DRC, reg32); /* Set initialization complete */ - PRINT_DEBUG("Setting initialization complete\r\n"); + PRINT_DEBUG("Setting initialization complete\n"); reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 |= (RAM_COMMAND_IC << 29); pci_write_config32(NORTHBRIDGE, DRC, reg32); @@ -568,6 +568,6 @@ static void sdram_initialize(void) /* Setup Initial Northbridge Registers */ northbridge_set_registers(); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); } diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index 4083add6f1..40da896589 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -60,7 +60,7 @@ static void print_pci_devices(void) continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -68,7 +68,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -80,7 +80,7 @@ static void dump_pci_device(unsigned dev) print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -105,7 +105,7 @@ static void dump_pci_devices(void) static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 2; i++) { unsigned device; device = ctrl->channel0[i]; @@ -119,20 +119,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } #if 0 device = ctrl->channel1[i]; @@ -146,20 +146,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } #endif } @@ -167,7 +167,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) static void dump_smbus_registers(void) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 1; i < 0x80; i++) { unsigned device; device = i; @@ -178,20 +178,20 @@ static void dump_smbus_registers(void) int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } #endif diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 8e928bd279..136266da2c 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -31,7 +31,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { /* - print_debug("Before configuration:\r\n"); + print_debug("Before configuration:\n"); dump_pci_devices(); */ } @@ -212,7 +212,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl, adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9)); print_debug("Setting mode: "); print_debug_hex32(adjusted_mode + addr); - print_debug("\r\n"); + print_debug("\n"); read32(adjusted_mode + addr); } @@ -229,39 +229,39 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; uint32_t rank1 = (1 << 30) / 2; - print_debug("Ram enable 1\r\n"); + print_debug("Ram enable 1\n"); delay(); delay(); - print_debug("Ram enable 2\r\n"); + print_debug("Ram enable 2\n"); ram_command(ctrl, 1, 0); ram_command(ctrl, 1, rank1); delay(); delay(); - print_debug("Ram enable 3\r\n"); + print_debug("Ram enable 3\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - print_debug("Ram enable 4\r\n"); + print_debug("Ram enable 4\n"); ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0); ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1); delay(); delay(); - print_debug("Ram enable 5\r\n"); + print_debug("Ram enable 5\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1); - print_debug("Ram enable 6\r\n"); + print_debug("Ram enable 6\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - print_debug("Ram enable 7\r\n"); + print_debug("Ram enable 7\n"); for(i = 0; i < 8; i++) { ram_command(ctrl, 6, 0); ram_command(ctrl, 6, rank1); @@ -269,28 +269,28 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) delay(); } - print_debug("Ram enable 8\r\n"); + print_debug("Ram enable 8\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1); - print_debug("Ram enable 9\r\n"); + print_debug("Ram enable 9\n"); ram_command(ctrl, 7, 0); ram_command(ctrl, 7, rank1); delay(); delay(); - print_debug("Ram enable 9\r\n"); + print_debug("Ram enable 9\n"); set_initialize_complete(ctrl); delay(); delay(); delay(); - print_debug("After configuration:\r\n"); + print_debug("After configuration:\n"); /* dump_pci_devices(); */ /* - print_debug("\n\n***** RAM TEST *****\r\n"); + print_debug("\n\n***** RAM TEST *****\n"); ram_check(0, 0xa0000); ram_check(0x100000, 0x40000000); */ diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index 577d53b05b..7f7c997077 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -151,7 +151,7 @@ static void ddr_ram_setup(void) unsigned long bank_address; - print_debug("CN400 RAM init starting\r\n"); + print_debug("CN400 RAM init starting\n"); pci_write_config8(ctrl.d0f7, 0x75, 0x08); @@ -176,7 +176,7 @@ static void ddr_ram_setup(void) */ c = 0; b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM); - //print_val("Detecting Memory\r\nNumber of Banks ",b); + //print_val("Detecting Memory\nNumber of Banks ",b); // Only supporting 4 bank chips just now if( b == 4 ){ @@ -186,7 +186,7 @@ static void ddr_ram_setup(void) c = 0x01; bank = 0x40; b = smbus_read_byte(0x50, SPD_NUM_ROWS); - //print_val("\r\nNumber of Rows ", b); + //print_val("\nNumber of Rows ", b); if( b >= 0x0d ){ // 256/512Mb @@ -199,7 +199,7 @@ static void ddr_ram_setup(void) Read SPD byte 13, Primary DRAM width. */ b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH); - //print_val("\r\nPrimary DRAM width", b); + //print_val("\nPrimary DRAM width", b); if( b != 4 ) // not 64/128Mb (x4) c = 0x81; // 256Mb } @@ -208,12 +208,12 @@ static void ddr_ram_setup(void) Read SPD byte 4, Number of column addresses. */ b = smbus_read_byte(0x50, SPD_NUM_COLUMNS); - //print_val("\r\nNo Columns ",b); + //print_val("\nNo Columns ",b); if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr if( b == 9 ) c |= 0x40; // 9 bit col addr if( b == 8 ) c |= 0x20; // 8 bit col addr - //print_val("\r\nMA type ", c); + //print_val("\nMA type ", c); pci_write_config8(ctrl.d0f3, 0x50, c); } @@ -223,7 +223,7 @@ static void ddr_ram_setup(void) /* else { - die("DRAM module size is not supported by CN400\r\n"); + die("DRAM module size is not supported by CN400\n"); } */ @@ -281,7 +281,7 @@ static void ddr_ram_setup(void) // SPD byte 5 # of physical banks b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS); - //print_val("\r\nNo Physical Banks ",b); + //print_val("\nNo Physical Banks ",b); if( b == 2) { c <<=1; @@ -289,7 +289,7 @@ static void ddr_ram_setup(void) } /* else { - die("Only a single DIMM is supported by EPIA-N(L)\r\n"); + die("Only a single DIMM is supported by EPIA-N(L)\n"); } */ // set banks 1,2,3... @@ -309,7 +309,7 @@ static void ddr_ram_setup(void) /* Read SPD byte 18 CAS Latency */ b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES); -/* print_debug("\r\nCAS Supported "); +/* print_debug("\nCAS Supported "); if(b & 0x04) print_debug("2 "); if(b & 0x08) @@ -318,11 +318,11 @@ static void ddr_ram_setup(void) print_debug("3"); c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - print_val("\r\nCycle time at CL X (nS)", c); + print_val("\nCycle time at CL X (nS)", c); c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND); - print_val("\r\nCycle time at CL X-0.5 (nS)", c); + print_val("\nCycle time at CL X-0.5 (nS)", c); c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD); - print_val("\r\nCycle time at CL X-1 (nS)", c); + print_val("\nCycle time at CL X-1 (nS)", c); */ /* Scaling of Cycle Time SPD data */ /* 7 4 3 0 */ @@ -330,27 +330,27 @@ static void ddr_ram_setup(void) bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if( b & 0x10 ){ // DDR offering optional CAS 3 - //print_debug("\r\nStarting at CAS 3"); + //print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5 - //print_debug("\r\nWe can do CAS 2.5"); + //print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2 - //print_debug("\r\nWe can do CAS 2"); + //print_debug("\nWe can do CAS 2"); c = 0x10; } } }else{ // no optional CAS values just 2 & 2.5 - //print_debug("\r\nStarting at CAS 2.5"); + //print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 - //print_debug("\r\nWe can do CAS 2"); + //print_debug("\nWe can do CAS 2"); c = 0x10; } } @@ -386,7 +386,7 @@ static void ddr_ram_setup(void) b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME); - //print_val("\r\ntRP ",b); + //print_val("\ntRP ",b); if ( b >= (5 * bank)) { c |= 0x03; // set tRP = 5T } @@ -404,7 +404,7 @@ static void ddr_ram_setup(void) */ b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY); - //print_val("\r\ntRCD ",b); + //print_val("\ntRCD ",b); if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T @@ -421,8 +421,8 @@ static void ddr_ram_setup(void) bank = bank >> 2; b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - //print_val("\r\ntRAS ",b); - //print_val("\r\nBank ", bank); + //print_val("\ntRAS ",b); + //print_val("\nBank ", bank); if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T @@ -537,7 +537,7 @@ static void ddr_ram_setup(void) c &= 0x08; if ( c == 0x08 ) { - print_debug("Setting Burst Length 8\r\n"); + print_debug("Setting Burst Length 8\n"); /* CPU Frequency Device 0 Function 2 Offset 54 @@ -723,7 +723,7 @@ static void ddr_ram_setup(void) break; } - print_val("\r\nLow Bond ",i); + print_val("\nLow Bond ",i); if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ @@ -767,7 +767,7 @@ static void ddr_ram_setup(void) print_val(" High Bond ",i); c = ((i - c)<<1)/3 + c; print_val(" Setting DQS delay",c); - print_debug("\r\n"); + print_debug("\n"); pci_write_config8(ctrl.d0f3,0x70,c); }else{ pci_write_config8(ctrl.d0f3,0x70,0x67); @@ -822,5 +822,5 @@ static void ddr_ram_setup(void) /* VGA device. */ pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15)); pci_write_config16(ctrl.d0f3, 0xa4, 0x0010); - print_debug("CN400 raminit.c done\r\n"); + print_debug("CN400 raminit.c done\n"); } diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index bddb4448fe..72fb0c5a26 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -183,7 +183,7 @@ static void sdram_set_size(const struct mem_controller *ctrl) } if (result == 0xff) - die("DRAM module size too big, not supported by CN700\r\n"); + die("DRAM module size too big, not supported by CN700\n"); pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x48, 0x00); @@ -389,30 +389,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address) u8 i; /* 1. Apply NOP. */ - PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n"); do_ram_command(dev, RAM_COMMAND_NOP); udelay(100); read32(rank_address + 0x10); /* 2. Precharge all. */ udelay(400); - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x10); /* 3. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); do_ram_command(dev, RAM_COMMAND_MRS); read32(rank_address + 0x120000); /* EMRS DLL Enable */ read32(rank_address + 0x800); /* MRS DLL Reset */ /* 4. Precharge all again. */ - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x0); /* 5. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG_MEM("RAM Enable 3: CBR\n"); do_ram_command(dev, RAM_COMMAND_CBR); for (i = 0; i < 8; i++) { read32(rank_address + 0x20); @@ -420,7 +420,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) } /* 6. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but @@ -433,7 +433,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */ /* 8. Normal operation */ - PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n"); do_ram_command(dev, RAM_COMMAND_NORMAL); read32(rank_address + 0x30); } diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c index ccee3b4633..361b5e9bca 100644 --- a/src/northbridge/via/cx700/cx700_early_smbus.c +++ b/src/northbridge/via/cx700/cx700_early_smbus.c @@ -66,25 +66,25 @@ static void smbus_print_error(unsigned char host_status_register, int loops) print_err("SMBus Error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (loops >= SMBUS_TIMEOUT) { - print_err("SMBus Timout\r\n"); + print_err("SMBus Timout\n"); } if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { /* This isn't a real error... */ - print_debug("Interrupt/SMI# was Successful Completion\r\n"); + print_debug("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } @@ -240,7 +240,7 @@ static void dump_spd_data(const struct mem_controller *ctrl) for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); - print_debug("\r\n"); + print_debug("\n"); val = get_spd_data(ctrl, dimm, 0); if (val == 0xff) { @@ -248,7 +248,7 @@ static void dump_spd_data(const struct mem_controller *ctrl) } else if (val == 0x80) { regs = 128; } else { - print_debug("No DIMM present\r\n"); + print_debug("No DIMM present\n"); regs = 0; } for (offset = 0; offset < regs; offset++) { @@ -256,7 +256,7 @@ static void dump_spd_data(const struct mem_controller *ctrl) print_debug_hex8(offset); print_debug(" = 0x"); print_debug_hex8(get_spd_data(ctrl, dimm, offset)); - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c index 65c8088e68..2042d62d27 100644 --- a/src/northbridge/via/vt8601/raminit.c +++ b/src/northbridge/via/vt8601/raminit.c @@ -79,7 +79,7 @@ void dumpnorth(device_t north) print_debug_hex8(pci_read_config8(north, r + c)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); if (r >= 240) break; } @@ -90,13 +90,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) device_t north = (device_t) PCI_DEV(0, 0, 0); uint8_t c, r; - print_err("vt8601 init starting\r\n"); + print_err("vt8601 init starting\n"); print_debug_hex32(north); print_debug(" is the north\n"); print_debug_hex16(pci_read_config16(north, 0)); print_debug(" "); print_debug_hex16(pci_read_config16(north, 2)); - print_debug("\r\n"); + print_debug("\n"); /* All we are doing now is setting initial known-good values that will * be revised later as we read SPD @@ -186,7 +186,7 @@ static unsigned long spd_module_size(unsigned char slot) print_info("Slot "); print_info_hex8(slot); if (smbus_read_byte(module, 2) != 4) { - print_info(" is empty\r\n"); + print_info(" is empty\n"); return 0; } print_info(" is SDRAM "); @@ -211,7 +211,7 @@ static unsigned long spd_module_size(unsigned char slot) print_info("x2"); value = (value << 16) | value; } - print_info("\r\n"); + print_info("\n"); return value; } @@ -288,19 +288,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* set NOP */ pci_write_config8(north, 0x6C, 0x01); - print_debug("NOP\r\n"); + print_debug("NOP\n"); /* wait 200us */ // You need to do the memory reference. That causes the nop cycle. dimms_read(0); udelay(400); - print_debug("PRECHARGE\r\n"); + print_debug("PRECHARGE\n"); /* set precharge */ pci_write_config8(north, 0x6C, 0x02); - print_debug("DUMMY READS\r\n"); + print_debug("DUMMY READS\n"); /* dummy reads */ dimms_read(0); udelay(200); - print_debug("CBR\r\n"); + print_debug("CBR\n"); /* set CBR */ pci_write_config8(north, 0x6C, 0x04); @@ -321,7 +321,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) udelay(200); dimms_read(0); udelay(200); - print_debug("MRS\r\n"); + print_debug("MRS\n"); /* set MRS */ pci_write_config8(north, 0x6c, 0x03); #if DIMM_CL2 @@ -330,21 +330,21 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dimms_read(0x1d0); #endif udelay(200); - print_debug("NORMAL\r\n"); + print_debug("NORMAL\n"); /* set to normal mode */ pci_write_config8(north, 0x6C, 0x08); dimms_write(0x55aa55aa); dimms_read(0); udelay(200); - print_debug("set ref. rate\r\n"); + print_debug("set ref. rate\n"); // Set the refresh rate. #if DIMM_PC133 pci_write_config8(north, 0x6A, 0x86); #else pci_write_config8(north, 0x6A, 0x65); #endif - print_debug("enable multi-page open\r\n"); + print_debug("enable multi-page open\n"); // enable multi-page open pci_write_config8(north, 0x6B, 0x0d); @@ -381,8 +381,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* 256MB or more per side */ ma = 0xe; print_debug_hex16(ma); - print_debug(" is the MA type\r\n"); + print_debug(" is the MA type\n"); set_ma_mapping(north, slot, ma); } - print_err("vt8601 done\r\n"); + print_err("vt8601 done\n"); } diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c index ffae808936..40338dae7e 100644 --- a/src/northbridge/via/vt8623/raminit.c +++ b/src/northbridge/via/vt8623/raminit.c @@ -56,7 +56,7 @@ dumpnorth(device_t north) print_debug_hex8(pci_read_config8(north, r+c)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } } void print_val(char *str, int val) @@ -72,7 +72,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) uint16_t i,j; unsigned long bank_address; - print_debug("vt8623 init starting\r\n"); + print_debug("vt8623 init starting\n"); north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0); north = 0; @@ -102,7 +102,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) */ c = 0; b = smbus_read_byte(0xa0,17); - print_val("Detecting Memory\r\nNumber of Banks ",b); + print_val("Detecting Memory\nNumber of Banks ",b); if( b != 2 ){ // not 16 Mb type @@ -110,14 +110,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) Read SPD byte 3, Number of row addresses. */ b = smbus_read_byte(0xa0,3); - print_val("\r\nNumber of Rows ",b); + print_val("\nNumber of Rows ",b); if( b >= 0x0d ){ // not 64/128Mb (rows <=12) /* Read SPD byte 13, Primary DRAM width. */ b = smbus_read_byte(0xa0,13); - print_val("\r\nPriamry DRAM width",b); + print_val("\nPriamry DRAM width",b); if( b != 4 ) // mot 64/128Mb (x4) c = 0x80; // 256Mb } @@ -128,13 +128,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) Read SPD byte 4, Number of column addresses. */ b = smbus_read_byte(0xa0,4); - print_val("\r\nNo Columns ",b); + print_val("\nNo Columns ",b); if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr if( b == 9 ) c |= 0x40; // 9 bit col addr if( b == 8 ) c |= 0x20; // 8 bit col addr } - print_val("\r\nMA type ",c); + print_val("\nMA type ",c); pci_write_config8(north,0x58,c); /* @@ -161,18 +161,18 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) else c = 0x01; // Error, use default - print_val("\r\nBank 0 (*16 Mb) ",c); + print_val("\nBank 0 (*16 Mb) ",c); // set bank zero size pci_write_config8(north,0x5a,c); // SPD byte 5 # of physical banks b = smbus_read_byte(0xa0,5); - print_val("\r\nNo Physical Banks ",b); + print_val("\nNo Physical Banks ",b); if( b == 2) c <<=1; - print_val("\r\nTotal Memory (*16 Mb) ",c); + print_val("\nTotal Memory (*16 Mb) ",c); // set banks 1,2,3 pci_write_config8(north,0x5b,c); pci_write_config8(north,0x5c,c); @@ -181,40 +181,40 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) /* Read SPD byte 18 CAS Latency */ b = smbus_read_byte(0xa0,18); - print_debug("\r\nCAS Supported "); + print_debug("\nCAS Supported "); if(b & 0x04) print_debug("2 "); if(b & 0x08) print_debug("2.5 "); if(b & 0x10) print_debug("3"); - print_val("\r\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); - print_val("\r\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); - print_val("\r\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); + print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); + print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); + print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); if( b & 0x10 ){ // DDR offering optional CAS 3 - print_debug("\r\nStarting at CAS 3"); + print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5 - print_debug("\r\nWe can do CAS 2.5"); + print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2 - print_debug("\r\nWe can do CAS 2"); + print_debug("\nWe can do CAS 2"); c = 0x10; } } }else{ // no optional CAS values just 2 & 2.5 - print_debug("\r\nStarting at CAS 2.5"); + print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2 - print_debug("\r\nWe can do CAS 2"); + print_debug("\nWe can do CAS 2"); c = 0x10; } } @@ -254,7 +254,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) */ b = smbus_read_byte(0xa0,27); - print_val("\r\ntRP ",b); + print_val("\ntRP ",b); if( b > 0x3c ) // set tRP = 3T c |= 0x80; @@ -266,7 +266,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) */ b = smbus_read_byte(0xa0,29); - print_val("\r\ntRCD ",b); + print_val("\ntRCD ",b); if( b > 0x3c ) // set tRCD = 3T c |= 0x04; @@ -278,7 +278,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) */ b = smbus_read_byte(0xa0,30); - print_val("\r\ntRAS ",b); + print_val("\ntRAS ",b); if( b > 0x25 ) // set tRAS = 6T c |= 0x40; @@ -500,7 +500,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) break; } - print_val("\r\nLow Bond ",i); + print_val("\nLow Bond ",i); if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ @@ -549,7 +549,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) pci_write_config8(north,0x68,c); pci_write_config8(north,0x68,0x42); }else{ - print_debug("Unable to determine low bond - Setting default\r\n"); + print_debug("Unable to determine low bond - Setting default\n"); pci_write_config8(north,0x68,0x59); } @@ -608,10 +608,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) pci_write_config8(north,0xac,0x2f); pci_write_config8(north,0xae,0x04); - print_debug("vt8623 done\r\n"); + print_debug("vt8623 done\n"); dumpnorth(north); - print_debug("AGP\r\n"); + print_debug("AGP\n"); north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0); pci_write_config32(north,0x20,0xddf0dc00); pci_write_config32(north,0x24,0xdbf0d800); diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 80ee22c22a..22c0fbd40f 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -52,13 +52,13 @@ int acpi_is_wakeup_early_via_vx800(void) device_t dev; u16 tmp, result; - print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); + print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); @@ -70,7 +70,7 @@ int acpi_is_wakeup_early_via_vx800(void) result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; print_debug(" boot_mode="); print_debug_hex16(result); - print_debug("\r\n"); + print_debug("\n"); return result; } @@ -85,7 +85,7 @@ static void enable_mainboard_devices(void) device_t dev; uint16_t values; - print_debug("In enable_mainboard_devices \r\n"); + print_debug("In enable_mainboard_devices \n"); /* Enable P2P Bridge Header for External PCI BUS. @@ -375,14 +375,14 @@ g) Rx73h = 32h if (bist == 0) { // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); - //print_debug("doing early_mtrr\r\n"); + //print_debug("doing early_mtrr\n"); //early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); u8 Data; @@ -392,7 +392,7 @@ g) Rx73h = 32h Data = pci_read_config8(device, 0xf6); print_debug("NB chip revision ="); print_debug_hex8(Data); - print_debug("\r\n"); + print_debug("\n"); /* make NB ready before draminit */ via_pci_inittable(Data, mNbStage1InitTbl); @@ -405,7 +405,7 @@ g) Rx73h = 32h u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; DRAM_SYS_ATTR DramAttr; - print_debug("This is a S3 wakeup\r\n"); + print_debug("This is a S3 wakeup\n"); memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */ @@ -429,7 +429,7 @@ g) Rx73h = 32h DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here! SetUMARam(); // I just copy this function from draminit to here! - print_debug("Resume from S3, RAM init was ignored\r\n"); + print_debug("Resume from S3, RAM init was ignored\n"); } else { ddr2_ram_setup(); ram_check(0, 640 * 1024); @@ -528,7 +528,7 @@ g) Rx73h = 32h "rep movsd\n\t" ::"g"(memtop4) );*/ - print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); //this can have function call, because no variable used before this + print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), (unsigned char *) 0, 0xa0000); @@ -572,11 +572,11 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp) ); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); + printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); #else print_debug("v_esp="); print_debug_hex32(v_esp); - print_debug("\r\n"); + print_debug("\n"); #endif } @@ -588,11 +588,11 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav //stack cpu_reset = 0; #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); + printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); #else print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif if (cpu_reset == 0) { @@ -635,16 +635,16 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav /* We can not go back any more, we lost old stack data in cache as ram */ if (new_cpu_reset == 0) { - print_debug("Use Ram as Stack now - done\r\n"); + print_debug("Use Ram as Stack now - done\n"); } else { - print_debug("Use Ram as Stack now - \r\n"); + print_debug("Use Ram as Stack now - \n"); } #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); + printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif /*copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); @@ -653,6 +653,6 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav #endif - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 58d70c33c3..ee010a0c8b 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -102,7 +102,7 @@ static void vga_init(device_t dev) } #else /* Attempt to manually force the rom to load */ - printk(BIOS_DEBUG, "Forcing rom load\r\n"); + printk(BIOS_DEBUG, "Forcing rom load\n"); pci_rom_load(dev, 0xfff80000); run_bios(dev, 0xc0000); #endif diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c index 9beb9cf130..93b1461e9a 100644 --- a/src/northbridge/via/vx800/vx800_early_smbus.c +++ b/src/northbridge/via/vx800/vx800_early_smbus.c @@ -60,32 +60,32 @@ /* Internal functions */ static void smbus_print_error(unsigned char host_status_register, int loops) { -// print_err("some i2c error\r\n"); +// print_err("some i2c error\n"); /* Check if there actually was an error */ if (host_status_register == 0x00 || host_status_register == 0x40 || host_status_register == 0x42) return; print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (loops >= SMBUS_TIMEOUT) { - print_err("SMBus Timout\r\n"); + print_err("SMBus Timout\n"); } if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { /* This isn't a real error... */ - print_debug("Interrupt/SMI# was Successful Completion\r\n"); + print_debug("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } @@ -204,7 +204,7 @@ static void enable_smbus(void) if (dev == PCI_DEV_INVALID) { /* This won't display text if enable_smbus() is before serial init */ - die("Power Managment Controller not found\r\n"); + die("Power Managment Controller not found\n"); } /* Set clock source */ @@ -253,7 +253,7 @@ void smbus_fixup(const struct mem_controller *ctrl) ram_slots = ARRAY_SIZE(ctrl->channel0); if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\r\n"); + print_err("smbus_fixup() thinks there are no RAM slots!\n"); return; } @@ -279,9 +279,9 @@ void smbus_fixup(const struct mem_controller *ctrl) } if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\r\n"); + print_err("SMBus timed out while warming up\n"); else - PRINT_DEBUG("Done\r\n"); + PRINT_DEBUG("Done\n"); } /* Debugging Function */ @@ -294,7 +294,7 @@ static void dump_spd_data(void) for (dimm = 0; dimm < 8; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); - print_debug("\r\n"); + print_debug("\n"); val = get_spd_data(dimm, 0); if (val == 0xff) { @@ -302,7 +302,7 @@ static void dump_spd_data(void) } else if (val == 0x80) { regs = 128; } else { - print_debug("No DIMM present\r\n"); + print_debug("No DIMM present\n"); regs = 0; } for (offset = 0; offset < regs; offset++) { @@ -310,7 +310,7 @@ static void dump_spd_data(void) print_debug_hex8(offset); print_debug(" = 0x"); print_debug_hex8(get_spd_data(dimm, offset)); - print_debug("\r\n"); + print_debug("\n"); } } } diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index c8996784de..11aa6f750e 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -9,7 +9,7 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); @@ -23,7 +23,7 @@ static void enable_smbus(void) /* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); } static int smbus_recv_byte(unsigned device) diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c index c23426e086..583602c3dd 100644 --- a/src/southbridge/amd/cs5535/cs5535_early_setup.c +++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c @@ -164,19 +164,19 @@ static int cs5535_early_setup(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n\r"); + print_debug("reboot from BIOS reset\n"); return; } - print_debug("Setup idsel\r\n"); + print_debug("Setup idsel\n"); cs5535_setup_idsel(); - print_debug("Setup iobase\r\n"); + print_debug("Setup iobase\n"); cs5535_usb_swapsif(); cs5535_setup_iobase(); - print_debug("Setup gpio\r\n"); + print_debug("Setup gpio\n"); cs5535_setup_gpio(); - print_debug("Setup cis_mode\r\n"); + print_debug("Setup cis_mode\n"); cs5535_setup_cis_mode(); - print_debug("Setup smbus\r\n"); + print_debug("Setup smbus\n"); cs5535_enable_smbus(); dummy(); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c index 8a553f57e0..cd8bffa868 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_setup.c +++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c @@ -257,18 +257,18 @@ static void cs5536_early_setup(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - //print_debug("reboot from BIOS reset\n\r"); + //print_debug("reboot from BIOS reset\n"); return; } - //print_debug("Setup idsel\r\n"); + //print_debug("Setup idsel\n"); cs5536_setup_idsel(); - //print_debug("Setup iobase\r\n"); + //print_debug("Setup iobase\n"); cs5536_usb_swapsif(); cs5536_setup_iobase(); - //print_debug("Setup gpio\r\n"); + //print_debug("Setup gpio\n"); cs5536_setup_gpio(); - //print_debug("Setup smbus\r\n"); + //print_debug("Setup smbus\n"); cs5536_enable_smbus(); - //print_debug("Setup power button\r\n"); + //print_debug("Setup power button\n"); cs5536_setup_power_button(); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c index 298feeed9b..ce8e690567 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c +++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c @@ -199,7 +199,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base, print_debug_hex8(error); print_debug(" device:"); print_debug_hex8(device); - print_debug("\r\n"); + print_debug("\n"); /* stop, clean up the error, and leave */ smbus_stop_condition(smbus_io_base); outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c index b7581ec352..dd2ed69cd2 100644 --- a/src/southbridge/amd/sb600/sb600_early_setup.c +++ b/src/southbridge/amd/sb600/sb600_early_setup.c @@ -44,7 +44,7 @@ static u8 get_sb600_revision(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } return pci_read_config8(dev, 0x08); @@ -290,10 +290,10 @@ static void sb600_devices_por_init(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n", get_sb600_revision()); /* sbPorAtStartOfTblCfg */ diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index 3777bd6288..5d2fde2a4c 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -51,7 +51,7 @@ static u8 set_sb700_revision(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } rev_id = pci_read_config8(dev, 0x08); @@ -81,7 +81,7 @@ static u8 set_sb700_revision(void) } else if (rev_id == 0x3D) { rev = 0x15; } else - die("It is not SB700 or SB710\r\n"); + die("It is not SB700 or SB710\n"); return rev; } @@ -306,10 +306,10 @@ static void sb700_devices_por_init(void) dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", set_sb700_revision()); /* sbPorAtStartOfTblCfg */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c index b6a2fe506e..64b8d07245 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c @@ -13,10 +13,10 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index 136c03a88b..462d9edf2d 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -86,7 +86,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC case 0x64: diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c index 7cd9c27f35..e82fa3ca8e 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c @@ -53,13 +53,13 @@ static void sata_init(struct device *dev) for(i=0; i<4; i++) { mmio = base + 0x100 * i; byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c index 503d573dea..ae7cfcd227 100644 --- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c +++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c @@ -6,7 +6,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); @@ -92,7 +92,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; } diff --git a/src/southbridge/intel/i3100/i3100_early_smbus.c b/src/southbridge/intel/i3100/i3100_early_smbus.c index b7edb9b68c..79825d153a 100644 --- a/src/southbridge/intel/i3100/i3100_early_smbus.c +++ b/src/southbridge/intel/i3100/i3100_early_smbus.c @@ -26,7 +26,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c index 689dfed1d1..ada781ec26 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c +++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c @@ -38,9 +38,9 @@ static void enable_smbus(void) PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\r\n"); + die("SMBus controller not found\n"); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); /* Set the SMBus I/O base. */ pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h index e1893c5cb1..a1ede98eb6 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h +++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h @@ -192,7 +192,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned #if 0 print_debug("Read fail "); print_debug_hex16(status_register); - print_debug("\r\n"); + print_debug("\n"); #endif return SMBUS_ERROR; } diff --git a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c index d80c29c159..14fa924bea 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c +++ b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c @@ -58,7 +58,7 @@ static void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) @@ -69,7 +69,7 @@ static inline int smbus_read_byte(unsigned device, unsigned address) static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - print_err("Unimplemented smbus_write_byte() called\r\n"); + print_err("Unimplemented smbus_write_byte() called\n"); return; } diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h index 7a7850835b..e4ec70bc5f 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_smbus.h +++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.h @@ -116,7 +116,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { #warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\r\n"); + print_err("Untested smbus_write_block called\n"); #if 0 unsigned char global_control_register; unsigned char global_status_register; @@ -177,7 +177,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; #endif } diff --git a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c index 6a3d4947e8..cd0c20d98e 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c +++ b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c @@ -51,5 +51,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); } diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c index b8ec9b7528..66935661dd 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c +++ b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c @@ -58,7 +58,7 @@ static void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) @@ -69,7 +69,7 @@ static inline int smbus_read_byte(unsigned device, unsigned address) static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - print_err("Unimplemented smbus_write_byte() called\r\n"); + print_err("Unimplemented smbus_write_byte() called\n"); return; } diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h index 7a7850835b..e4ec70bc5f 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -116,7 +116,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { #warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\r\n"); + print_err("Untested smbus_write_block called\n"); #if 0 unsigned char global_control_register; unsigned char global_status_register; @@ -177,7 +177,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; #endif } diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c index fb45f521c5..fcb08a1a0c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c +++ b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c @@ -50,5 +50,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); } diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c index 9c3480283c..02420ef75b 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c @@ -5,7 +5,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c index 30d197c461..b36f03e83d 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c @@ -42,7 +42,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ @@ -119,7 +119,7 @@ static int smbus_read_byte(unsigned device, unsigned address) unsigned char global_status_register; unsigned char byte; - /*print_err("smbus_read_byte\r\n"); */ + /*print_err("smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { print_err_hex8(-2); return -2; @@ -169,7 +169,7 @@ static int smbus_read_byte(unsigned device, unsigned address) /* print_err("smbus_read_byte: "); print_err_hex32(device); print_err(" ad "); print_err_hex32(address); - print_err("value "); print_err_hex8(byte); print_err("\r\n"); + print_err("value "); print_err_hex8(byte); print_err("\n"); */ return byte; } diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index c86bf23bb7..0ad5c74ee0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -6,7 +6,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); print_debug_hex32(pci_read_config32(dev, 0x20)); @@ -35,7 +35,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va return; } - print_debug("Unimplemented smbus_write_byte() called.\r\n"); + print_debug("Unimplemented smbus_write_byte() called.\n"); #if 0 /* setup transaction */ @@ -125,7 +125,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; } diff --git a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c index 205ea87d94..26f6644763 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c +++ b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c @@ -24,6 +24,6 @@ void watchdog_off(void) /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n"); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } diff --git a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c b/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c index 7c0d97d2c8..7d3c80e8a7 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c +++ b/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c @@ -49,7 +49,7 @@ static void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\r\n"); + print_debug("SMBus controller enabled.\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c index 436a9227cd..a26786d7d0 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c +++ b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c @@ -49,5 +49,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH7 watchdog disabled\n"); } diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c index 2bf6732e79..db641415ff 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c +++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.c @@ -12,9 +12,9 @@ static void enable_smbus(void) device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\r\n"); + die("SMBus controller not found\n"); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* Set SMBus I/O base. */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index d68a5b1077..3458738f9b 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -250,7 +250,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); + printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c index 8eed906ce8..2a29689ad6 100644 --- a/src/southbridge/nvidia/ck804/ck804_sata.c +++ b/src/southbridge/nvidia/ck804/ck804_sata.c @@ -51,7 +51,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) return; dword = *(base + 0); - printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); if (dword == 0x113) { loop = 200000; // 2 do { @@ -60,11 +60,11 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); } dword = *(base + 0x40); - printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); if (dword == 0x113) { loop = 200000; //2 do { @@ -73,7 +73,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); } } #endif diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c index cee5f25a24..6d776d38bd 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c @@ -412,7 +412,7 @@ static int mcp55_early_setup_x(void) } out: - print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n"); + print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n"); mcp55_early_set_port(mcp55_num, busn, devn, io_base); mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x); diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c index e27664aa18..83ea61965b 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c @@ -33,10 +33,10 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); #if 0 if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); #endif /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1); diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/sis966_aza.c index 8e8f8e0055..60c99706fe 100644 --- a/src/southbridge/sis/sis966/sis966_aza.c +++ b/src/southbridge/sis/sis966/sis966_aza.c @@ -277,14 +277,14 @@ static void aza_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/southbridge/sis/sis966/sis966_ide.c b/src/southbridge/sis/sis966/sis966_ide.c index 1ee583f889..c57be5ade7 100644 --- a/src/southbridge/sis/sis966/sis966_ide.c +++ b/src/southbridge/sis/sis966/sis966_ide.c @@ -156,14 +156,14 @@ print_debug("IDE_INIT:---------->\n"); for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("IDE_INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c index 25853b03a4..b9cbf7a1be 100644 --- a/src/southbridge/sis/sis966/sis966_nic.c +++ b/src/southbridge/sis/sis966/sis966_nic.c @@ -270,7 +270,7 @@ static void nic_init(struct device *dev) if(!res) { - printk(BIOS_DEBUG, "NIC Cannot find resource..\r\n"); + printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); return; } base = res->base; @@ -278,7 +278,7 @@ static void nic_init(struct device *dev) if(!(val=phy_detect(base,&PhyAddr))) { - printk(BIOS_DEBUG, "PHY detect fail !!!!\r\n"); + printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; } @@ -321,14 +321,14 @@ static void nic_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } diff --git a/src/southbridge/sis/sis966/sis966_sata.c b/src/southbridge/sis/sis966/sis966_sata.c index 7fcee82f29..57a2d8870f 100644 --- a/src/southbridge/sis/sis966/sis966_sata.c +++ b/src/southbridge/sis/sis966/sis966_sata.c @@ -156,14 +156,14 @@ for (i=0;i<10;i++){ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/southbridge/sis/sis966/sis966_usb.c b/src/southbridge/sis/sis966/sis966_usb.c index e9761ba786..d49f2aabb4 100644 --- a/src/southbridge/sis/sis966/sis966_usb.c +++ b/src/southbridge/sis/sis966/sis966_usb.c @@ -81,14 +81,14 @@ static void usb_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("USB 1.1 INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/sis966_usb2.c index c2e5b9950b..6cb9873070 100644 --- a/src/southbridge/sis/sis966/sis966_usb2.c +++ b/src/southbridge/sis/sis966/sis966_usb2.c @@ -108,14 +108,14 @@ static void usb2_init(struct device *dev) for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("USB 2.0 INIT:<----------\n"); diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c index 1bfffed7f5..1083eb67e6 100644 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -39,7 +39,7 @@ static void enable_vt8231_serial(void) if (dev == PCI_DEV_INVALID) { outb(7, 0x80); - die("Serial controller not found\r\n"); + die("Serial controller not found\n"); } /* first, you have to enable the superio and superio config. diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index dbb6e213ae..34a1a5c5d8 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -30,7 +30,7 @@ static void enable_smbus(void) dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); @@ -47,9 +47,9 @@ static void enable_smbus(void) c |= 1; pci_write_config8(dev, 4, c); print_debug_hex8(c); - print_debug(" is the comm register\r\n"); + print_debug(" is the comm register\n"); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } @@ -117,7 +117,7 @@ void smbus_reset(void) smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\r\n"); + print_debug("\n"); } static void smbus_print_error(unsigned char host_status_register) @@ -125,21 +125,21 @@ static void smbus_print_error(unsigned char host_status_register) print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\r\n"); + print_err("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c index 8030f2f3df..9442b6e4d0 100644 --- a/src/southbridge/via/vt8235/vt8235_early_smbus.c +++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c @@ -36,7 +36,7 @@ static void enable_smbus(void) PCI_DEVICE_ID_VIA_8235), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE @@ -91,7 +91,7 @@ static int smbus_wait_until_ready(void) while((c & 1) == 1) { print_debug("c is "); print_debug_hex8(c); - print_debug("\r\n"); + print_debug("\n"); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); /* nop */ } @@ -110,7 +110,7 @@ void smbus_reset(void) smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\r\n"); + print_debug("\n"); } @@ -137,21 +137,21 @@ static void smbus_print_error(unsigned char host_status_register) print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\r\n"); + print_err("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index 17b32d529f..533cbe0c88 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -39,17 +39,17 @@ static void smbus_print_error(u8 host_status, int loops) return; if (loops >= SMBUS_TIMEOUT) - print_err("SMBus timeout\r\n"); + print_err("SMBus timeout\n"); if (host_status & (1 << 4)) - print_err("Interrupt/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrupt/SMI# was Failed Bus Transaction\n"); if (host_status & (1 << 3)) - print_err("Bus error\r\n"); + print_err("Bus error\n"); if (host_status & (1 << 2)) - print_err("Device error\r\n"); + print_err("Device error\n"); if (host_status & (1 << 1)) - print_debug("Interrupt/SMI# completed successfully\r\n"); + print_debug("Interrupt/SMI# completed successfully\n"); if (host_status & (1 << 0)) - print_err("Host busy\r\n"); + print_err("Host busy\n"); } /** @@ -59,7 +59,7 @@ static void smbus_wait_until_ready(void) { int loops; - PRINT_DEBUG("Waiting until SMBus ready\r\n"); + PRINT_DEBUG("Waiting until SMBus ready\n"); loops = 0; /* Yes, this is a mess, but it's the easiest way to do it. */ @@ -81,7 +81,7 @@ static void smbus_reset(void) PRINT_DEBUG("After reset status: "); PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } /** @@ -98,7 +98,7 @@ u8 smbus_read_byte(u8 dimm, u8 offset) PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); smbus_reset(); @@ -121,7 +121,7 @@ u8 smbus_read_byte(u8 dimm, u8 offset) val = inb(SMBHSTDAT0); PRINT_DEBUG("Read: "); PRINT_DEBUG_HEX16(val); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Probably don't have to do this, but it can't hurt. */ smbus_reset(); @@ -144,7 +144,7 @@ void enable_smbus(void) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); } /* @@ -189,7 +189,7 @@ void smbus_fixup(const struct mem_controller *ctrl) ram_slots = ARRAY_SIZE(ctrl->channel0); if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\r\n"); + print_err("smbus_fixup() thinks there are no RAM slots!\n"); return; } @@ -213,9 +213,9 @@ void smbus_fixup(const struct mem_controller *ctrl) } if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\r\n"); + print_err("SMBus timed out while warming up\n"); else - PRINT_DEBUG("Done\r\n"); + PRINT_DEBUG("Done\n"); } /* FIXME: Better separate the NB and SB, will be done once it works. */ @@ -310,7 +310,7 @@ int acpi_is_wakeup_early(void) { dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); } /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ @@ -337,7 +337,7 @@ void vt8237_early_spi_init(void) PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("SB not found\r\n"); + die("SB not found\n"); /* Put SPI base 20 d0 fe. */ tmp = pci_read_config32(dev, 0xbc); diff --git a/src/southbridge/via/vt82c686/vt82c686_early_serial.c b/src/southbridge/via/vt82c686/vt82c686_early_serial.c index e5aff02b8a..70c68aaaf5 100644 --- a/src/southbridge/via/vt82c686/vt82c686_early_serial.c +++ b/src/southbridge/via/vt82c686/vt82c686_early_serial.c @@ -65,7 +65,7 @@ static void vt82c686_enable_serial(device_t dev, unsigned iobase) if (sbdev == PCI_DEV_INVALID) { /* Serial output is not yet working at this point, but * die() emits the POST code 0xff and halts the CPU, too. */ - die("Southbridge not found.\r\n"); + die("Southbridge not found.\n"); } /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index e4ba7b4a55..fbc9185a1b 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -72,13 +72,13 @@ static void init_ec(uint16_t base) /* Read out current value of FAN_CTL control register (0x14). */ value = pnp_read_index(base, 0x14); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n", + printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", base + 0x14, value); /* Set FAN_CTL control register (0x14) polarity to high, and activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", + printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", base + 0x14, value | 0x87); } #endif diff --git a/src/superio/serverengines/pilot/pilot_early_init.c b/src/superio/serverengines/pilot/pilot_early_init.c index b5013ef306..08aa5a7624 100644 --- a/src/superio/serverengines/pilot/pilot_early_init.c +++ b/src/superio/serverengines/pilot/pilot_early_init.c @@ -33,9 +33,9 @@ static void pilot_early_init(device_t dev) print_debug("Using port: "); print_debug_hex16(port); - print_debug("\r\n"); + print_debug("\n"); pilot_disable_serial(PNP_DEV(port, 0x1)); - print_debug("disable serial 1\r\n"); + print_debug("disable serial 1\n"); /* pnp_enter_ext_func_mode(dev); diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 61ee12eaba..9756d36de7 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -195,7 +195,7 @@ static void pnp_exit_conf_state(device_t dev) static void dump_pnp_device(device_t dev) { int register_index; - print_debug("\r\n"); + print_debug("\n"); for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) { uint8_t register_value; @@ -214,10 +214,10 @@ static void dump_pnp_device(device_t dev) print_debug_char(' '); print_debug_hex8(register_value); if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 29826aa860..9df7ee9dc5 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -106,7 +106,7 @@ static void lpc47b397_pnp_enable_resources(device_t dev) switch(dev->path.pnp.device) { case LPC47B397_HWM: - printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\r\n"); + printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n"); pnp_set_logical_device(dev); enable_hwm_smbus(dev); break; diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 916590d4cf..001ac165dd 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -193,7 +193,7 @@ static void pnp_exit_conf_state(device_t dev) static void dump_pnp_device(device_t dev) { int register_index; - print_debug("\r\n"); + print_debug("\n"); for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) { uint8_t register_value; @@ -212,10 +212,10 @@ static void dump_pnp_device(device_t dev) print_debug_char(' '); print_debug_hex8(register_value); if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 4e6e6dcee9..cd4b539795 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -361,7 +361,7 @@ static void pnp_exit_conf_state(device_t dev) static void dump_pnp_device(device_t dev) { int register_index; - print_debug("\r\n"); + print_debug("\n"); for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) { uint8_t register_value; @@ -380,10 +380,10 @@ static void dump_pnp_device(device_t dev) print_debug_char(' '); print_debug_hex8(register_value); if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } - print_debug("\r\n"); + print_debug("\n"); } #endif diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 8deae4a683..45410d1ff4 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -100,7 +100,7 @@ static void init_hwm(unsigned long base) value = pnp_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; - /* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); */ + /* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value); */ pnp_write_index(base, reg, value); } } diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 7c470ae8a2..4c69a2c2c0 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -120,7 +120,7 @@ static void init_hwm(unsigned long base) value &= 0xff & hwm_reg_values[i+1]; value |= 0xff & hwm_reg_values[i+2]; #if 0 - printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); + printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value); #endif pnp_write_index(base, reg, value); } |