diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2018-03-23 18:49:01 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-04-09 16:43:08 +0000 |
| commit | 68a1542692f5674704ece3c4716924f30947a2a3 (patch) | |
| tree | c57fe9d2d2a5f0e249437aadd4b59723a4398cf1 | |
| parent | 5e32f41b438d92d47d777cb8df70c02ea45e8f70 (diff) | |
| download | coreboot-68a1542692f5674704ece3c4716924f30947a2a3.tar.xz | |
mb/google/octopus/variants/baseboard: Add DPTF parameters
This patch adds the DPTF parameters for Octopus baseboard.
These parameters are copied from reef/coral as initial reference values.
BUG=None
BRANCH=None
TEST=Build coreboot for Octopus board.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I069bae8c9ef43ebd1ee20945ef34a7f51991f621
Reviewed-on: https://review.coreboot.org/25339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl index 264ebb0403..140eb4bfd0 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -13,13 +13,70 @@ * GNU General Public License for more details. */ +/* Below values might change after Thermal Tuning. */ +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 120 +#define DPTF_TSR0_CRITICAL 125 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 46 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 58 +#define DPTF_TSR2_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER + /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ }) Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, }) Name (MPPC, Package () { + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } }) |