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author | Iru Cai <mytbk920423@gmail.com> | 2019-06-13 16:47:52 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-11-17 15:10:46 +0800 |
commit | 6b5e9839b68d819237bd781e83ea25f148b28395 (patch) | |
tree | 50b98be8cb4f2cd24050ff41fa7b1f3a74dbf375 | |
parent | 5d6bea3906aca0a0350e2664e1a7dd269b32b7f5 (diff) | |
download | coreboot-6b5e9839b68d819237bd781e83ea25f148b28395.tar.xz |
get_uma_size
-rw-r--r-- | src/northbridge/intel/haswell/Makefile.inc | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/me_uma.asm | 75 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/me_uma.c | 40 |
3 files changed, 45 insertions, 71 deletions
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b898ac72c5..cb0a0bd4dc 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -57,6 +57,7 @@ romstage-y += mrc_wdt.c romstage-y += pei_smbus.c romstage-y += mrc_frags.c romstage-y += pei_usb.c +romstage-y += me_uma.c postcar-y += memmap.c endif diff --git a/src/northbridge/intel/haswell/me_uma.asm b/src/northbridge/intel/haswell/me_uma.asm index 6f5d9acd79..a21c1b210a 100644 --- a/src/northbridge/intel/haswell/me_uma.asm +++ b/src/northbridge/intel/haswell/me_uma.asm @@ -4,6 +4,9 @@ global gPchMeUmaPpiGuid extern gEfiPeiStallPpiGuid extern mrc_sku_type extern gWdtPpiGuid +extern get_uma_size + +global fcn_fffbdf70 fcn_fffbdf70: ; not directly referenced push ebp @@ -325,76 +328,6 @@ pop esi pop ebp ret -fcn_fffc8c78: ; not directly referenced -push ebp -mov ebp, esp -push edi -push esi -push ebx -lea esp, [esp - 0x1c] -mov edi, dword [0xf00b0044] -mov eax, dword [0xf00b0040] -mov esi, dword [ebp + 8] -mov edx, eax -shr edx, 0x10 -and edx, 0xf -cmp dl, 2 -jne short loc_fffc8ca1 ; jne 0xfffc8ca1 - -loc_fffc8c9d: ; not directly referenced -xor eax, eax -jmp short loc_fffc8cfc ; jmp 0xfffc8cfc - -loc_fffc8ca1: ; not directly referenced -movzx eax, ah -test al, 0xf0 -jne short loc_fffc8c9d ; jne 0xfffc8c9d -sub esp, 0xc -lea edx, [ebp - 0x1c] -mov eax, dword [esi] -xor ebx, ebx -push edx -push 0 -push 0 -push gEfiPeiStallPpiGuid -push esi -call dword [eax + 0x20] ; ucall -add esp, 0x20 -jmp short loc_fffc8cdd ; jmp 0xfffc8cdd - -loc_fffc8cc5: ; not directly referenced -push edx -mov eax, dword [ebp - 0x1c] -inc ebx -push 0x3e8 -push eax -push esi -call dword [eax + 4] ; ucall -mov edi, dword [0xf00b0044] -add esp, 0x10 - -loc_fffc8cdd: ; not directly referenced -test edi, 0x10000 -jne short loc_fffc8cef ; jne 0xfffc8cef -cmp ebx, 0x1388 -jne short loc_fffc8cc5 ; jne 0xfffc8cc5 -jmp short loc_fffc8c9d ; jmp 0xfffc8c9d - -loc_fffc8cef: ; not directly referenced -cmp ebx, 0x1388 -je short loc_fffc8c9d ; je 0xfffc8c9d -mov eax, edi -and eax, 0x3f - -loc_fffc8cfc: ; not directly referenced -lea esp, [ebp - 0xc] -pop ebx -pop esi -pop edi -pop ebp -ret - - PchMeUmaDesc: dd 0x80000010 dd gPchMeUmaPpiGuid @@ -407,7 +340,7 @@ dd 0x859d7bb4 dd 0xd1c9f31d ref_fffcd514: -dd fcn_fffc8c78 +dd get_uma_size dd fcn_fffbe070 dd fcn_fffbe14d dd fcn_fffbe110 diff --git a/src/northbridge/intel/haswell/me_uma.c b/src/northbridge/intel/haswell/me_uma.c new file mode 100644 index 0000000000..7093e71f8d --- /dev/null +++ b/src/northbridge/intel/haswell/me_uma.c @@ -0,0 +1,40 @@ +#include <device/pci_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include "mrc_pei.h" +#include "mrc_utils.h" +#include <console/console.h> + +u32 get_uma_size(EFI_PEI_SERVICES **pps, void *me); +u32 get_uma_size(EFI_PEI_SERVICES **pps, void *me) +{ + int i = 0; + u32 me_uma; + u32 hfsts1; + + me_uma = pci_read_config32(PCH_ME_DEV, 0x44); + hfsts1 = pci_read_config32(PCH_ME_DEV, 0x40); + + if (((hfsts1 >> 16) & 0xf) == 2) + return 0; + + if (((hfsts1 >> 8) & 0xf0) != 0) + return 0; + + while ((me_uma & 0x10000) == 0) { + if (i == 5000) + return 0; + + i++; + usleep(1000); + me_uma = pci_read_config32(PCH_ME_DEV, 0x44); + } + + if (i != 5000) { + /* returns Intel ME UMA size */ + u32 sz = me_uma & 0x3f; + printk(BIOS_DEBUG, "ME UMA Size is %dMB.\n", sz); + return sz; + } else { + return 0; + } +} |