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authorIru Cai <mytbk920423@gmail.com>2018-12-28 15:56:57 +0800
committerIru Cai <mytbk920423@gmail.com>2019-11-17 15:10:45 +0800
commit70d1c1d4c5f803eb171dddf5eaf7fda7c6dbcad5 (patch)
treef6679c44f9b8b5b7b750e279162c49f1573ed0f1
parent9f61e6a01b8d720600c50cda2cea52b0c22fe205 (diff)
downloadcoreboot-70d1c1d4c5f803eb171dddf5eaf7fda7c6dbcad5.tar.xz
frag_fffa5d3c, frag_fffa627c
-rw-r--r--src/northbridge/intel/haswell/Makefile.inc1
-rw-r--r--src/northbridge/intel/haswell/mrc.asm51
-rw-r--r--src/northbridge/intel/haswell/mrc_frags.c40
3 files changed, 58 insertions, 34 deletions
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 73b4621ed1..4002480885 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -56,6 +56,7 @@ romstage-y += do_raminit_frag.c
romstage-y += mrc_frag_init_memory.c
romstage-y += mrc_wdt.c
romstage-y += pei_smbus.c
+romstage-y += mrc_frags.c
postcar-y += memmap.c
endif
diff --git a/src/northbridge/intel/haswell/mrc.asm b/src/northbridge/intel/haswell/mrc.asm
index cec9cc930f..fb7a0e93c1 100644
--- a/src/northbridge/intel/haswell/mrc.asm
+++ b/src/northbridge/intel/haswell/mrc.asm
@@ -177,6 +177,10 @@ extern frag_fffa549a
extern mrc_wdt_ppi
+;; other frags
+extern frag_fffa5d3c
+extern frag_fffa627c
+
;;
mrc_entry:
@@ -3537,19 +3541,13 @@ jne short loc_fffa5d22 ; jne 0xfffa5d22
jmp near loc_fffa5e1e ; jmp 0xfffa5e1e
loc_fffa5d3c: ; not directly referenced
-mov edx, dword [ebx + 0x103f]
mov dword [ebp - 0x84], 0
-add edx, eax
-mov dword [edx], 0x200c040
-mov edx, dword [ebx + 0x103f]
-lea edx, [eax + edx + 0x10]
-mov dword [edx], 0x88888888
-mov edx, dword [ebx + 0x103f]
-lea edx, [eax + edx + 0x20]
-mov dword [edx], 0x3b08060
-mov edx, dword [ebx + 0x103f]
-lea edx, [eax + edx + 0x30]
-mov dword [edx], 0x88888888
+
+push eax
+push dword [ebx + 0x103f]
+call frag_fffa5d3c
+add esp, 8
+
imul edx, edi, 0x12
add edx, 0x220
mov dword [ebp - 0x7c], edx
@@ -3877,28 +3875,13 @@ add ecx, dword [ebx + 0x103f]
mov byte [ecx], 0x60
loc_fffa627c: ; not directly referenced
-mov ecx, dword [ebx + 0x103f]
-add ecx, eax
-mov dword [ecx], 0xc183060
-mov ecx, dword [ebx + 0x103f]
-lea ecx, [eax + ecx + 0x2210]
-mov dword [ecx], 0x8102040
-mov ecx, dword [ebx + 0x103f]
-lea ecx, [eax + ecx + 0x604]
-mov dword [ecx], 0x8102040
-mov byte [edx + 0x2fd], 0x40
-mov byte [edx + 0x2fe], 0x40
-mov byte [edx + 0x2ff], 0x40
-mov byte [edx + 0x300], 0x40
-mov edx, dword [ebx + 0x103f]
-lea edx, [eax + edx + 0x1ffc]
-mov dword [edx], 0
-mov edx, dword [ebx + 0x103f]
-lea edx, [eax + edx + 0x220c]
-mov dword [edx], 0
-mov edx, dword [ebx + 0x103f]
-lea edx, [eax + edx + 0x600]
-mov dword [edx], 0
+push eax ; save it
+push edx
+push eax
+push dword [ebx + 0x103f]
+call frag_fffa627c
+add esp, 12
+pop eax
loc_fffa6305: ; not directly referenced
inc dword [ebp - 0x78]
diff --git a/src/northbridge/intel/haswell/mrc_frags.c b/src/northbridge/intel/haswell/mrc_frags.c
new file mode 100644
index 0000000000..649d640695
--- /dev/null
+++ b/src/northbridge/intel/haswell/mrc_frags.c
@@ -0,0 +1,40 @@
+// other random frags extracted from mrc
+//
+#include <arch/pci_ops.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <console/console.h>
+#include "mrc_utils.h"
+#include "mrc_pei.h"
+
+void frag_fffa5d3c(void *bar, uint32_t offset);
+void frag_fffa5d3c(void *bar, uint32_t offset)
+{
+ /* [ebx + 0x103f] is 0xfed10000 (DEFAULT_MCHBAR)
+ printk(BIOS_DEBUG, "[ebx + 0x103f] is 0x%08x.\n",
+ (uint32_t)bar);
+ */
+ write32(bar + offset, 0x200c040);
+ write32(bar + offset + 0x10, 0x88888888);
+ write32(bar + offset + 0x20, 0x3b08060);
+ write32(bar + offset + 0x30, 0x88888888);
+}
+
+void frag_fffa627c(void *mchbar, uint32_t eax, void * edx);
+void frag_fffa627c(void *mchbar, uint32_t eax, void * edx)
+{
+ /* mchbar, edx is 0xff7fd266, 0xff7fe5ad (in stack)
+ printk(BIOS_DEBUG, "[ebx + 0x103f] is 0x%08x, edx is 0x%08x.\n",
+ (uint32_t)mchbar, (uint32_t)edx);
+ */
+
+ write32(mchbar + eax, 0xc183060);
+ write32(mchbar + eax + 0x2210, 0x8102040);
+ write32(mchbar + eax + 0x604, 0x8102040);
+ write8(edx + 0x2fd, 0x40);
+ write8(edx + 0x2fe, 0x40);
+ write8(edx + 0x2ff, 0x40);
+ write8(edx + 0x300, 0x40);
+ write32(mchbar + eax + 0x1ffc, 0);
+ write32(mchbar + eax + 0x220c, 0);
+ write32(mchbar + eax + 0x600, 0);
+}