google/gru: improve eye diagram for passing the test

The children of Gru should share the benefits. In the real world, Bob can't
pass the eye diagram tests.

BUG=chrome-os-partner:62714
BRANCH=firmware-gru-8785.B
TEST=build coreboot

Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd
Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/440745
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/441468
Reviewed-on: https://review.coreboot.org/18461
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 45 insertions, 47 deletions

diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 4dc677cb53..5926e492cf 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -253,53 +253,51 @@ static void setup_usb(void)
 	write32(&rk3399_grf->usbphy0_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
 	write32(&rk3399_grf->usbphy1_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3));
 
-	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) {
-		/* Set max pre-emphasis level, only on Kevin PHY0 and PHY1. */
-		write32(&rk3399_grf->usbphy0_ctrl[12],
-			RK_CLRSETBITS(0xffff, 0xa7));
-		write32(&rk3399_grf->usbphy1_ctrl[12],
-			RK_CLRSETBITS(0xffff, 0xa7));
-
-		/*
-		 * Disable the pre-emphasize in eop state and chirp
-		 * state to avoid mis-trigger the disconnect detection
-		 * and also avoid high-speed handshake fail for PHY0
-		 * and PHY1 consist of otg-port and host-port.
-		 */
-		write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3));
-		write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3));
-		write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3));
-		write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3));
-
-		/*
-		 * ODT auto compensation bypass, and set max driver
-		 * strength only for PHY0 and PHY1 otg-port.
-		 */
-		write32(&rk3399_grf->usbphy0_ctrl[2],
-			RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
-		write32(&rk3399_grf->usbphy1_ctrl[2],
-			RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
-
-		/*
-		 * ODT auto refresh bypass, and set the max bias current
-		 * tuning reference only for PHY0 and PHY1 otg-port.
-		 */
-		write32(&rk3399_grf->usbphy0_ctrl[3],
-			RK_CLRSETBITS(0x21c, 1 << 4));
-		write32(&rk3399_grf->usbphy1_ctrl[3],
-			RK_CLRSETBITS(0x21c, 1 << 4));
-
-		/*
-		 * ODT auto compensation bypass, and set default driver
-		 * strength only for PHY0 and PHY1 host-port.
-		 */
-		write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10));
-		write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10));
-
-		/* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */
-		write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9));
-		write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9));
-	}
+	/* Set max pre-emphasis level on PHY0 and PHY1. */
+	write32(&rk3399_grf->usbphy0_ctrl[12],
+		RK_CLRSETBITS(0xffff, 0xa7));
+	write32(&rk3399_grf->usbphy1_ctrl[12],
+		RK_CLRSETBITS(0xffff, 0xa7));
+
+	/*
+	 * Disable the pre-emphasize in eop state and chirp
+	 * state to avoid mis-trigger the disconnect detection
+	 * and also avoid high-speed handshake fail for PHY0
+	 * and PHY1 consist of otg-port and host-port.
+	 */
+	write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3));
+	write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3));
+	write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3));
+	write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3));
+
+	/*
+	 * ODT auto compensation bypass, and set max driver
+	 * strength only for PHY0 and PHY1 otg-port.
+	 */
+	write32(&rk3399_grf->usbphy0_ctrl[2],
+		RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
+	write32(&rk3399_grf->usbphy1_ctrl[2],
+		RK_CLRSETBITS(0x7e << 4, 0x60 << 4));
+
+	/*
+	 * ODT auto refresh bypass, and set the max bias current
+	 * tuning reference only for PHY0 and PHY1 otg-port.
+	 */
+	write32(&rk3399_grf->usbphy0_ctrl[3],
+		RK_CLRSETBITS(0x21c, 1 << 4));
+	write32(&rk3399_grf->usbphy1_ctrl[3],
+		RK_CLRSETBITS(0x21c, 1 << 4));
+
+	/*
+	 * ODT auto compensation bypass, and set default driver
+	 * strength only for PHY0 and PHY1 host-port.
+	 */
+	write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10));
+	write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10));
+
+	/* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */
+	write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9));
+	write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9));
 
 	setup_usb_otg0();
 	setup_usb_otg1();