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| author | Iru Cai <mytbk920423@gmail.com> | 2017-07-28 23:40:44 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-05 14:25:15 +0000 |
| commit | a0ad6e7873188ddb3a096d49548a7464450f914b (patch) | |
| tree | 570e4481bbba787f33e7b78993d028c8ac114bc5 | |
| parent | 13a500a404083c250e28816a394ee8d2849f4028 (diff) | |
| download | coreboot-a0ad6e7873188ddb3a096d49548a7464450f914b.tar.xz | |
northbridge/amd/lx: Fix function setShadowRCONF
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical
`&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise
`&`.
Also fix off-by-one error with the bitmasks.
Change-Id: I7d7720121d4730254542372282f5561739e7214b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20808
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/amd/lx/northbridgeinit.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index f588ead56a..1315b2aba2 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -485,18 +485,18 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) shadowByte = (uint8_t) (shadowLo >> 16); // load up D000 settings in edx. - for (bit = 8; (bit > 4); bit--) { + for (bit = 7; bit >= 4; bit--) { msr.hi <<= 8; msr.hi |= 1; // cache disable PCI/Shadow memory - if (shadowByte && (1 << bit)) + if (shadowByte & (1 << bit)) msr.hi |= 0x20; // write serialize PCI memory } // load up C000 settings in eax. - for (; bit; bit--) { + for (; bit >= 0; bit--) { msr.lo <<= 8; msr.lo |= 1; // cache disable PCI/Shadow memory - if (shadowByte && (1 << bit)) + if (shadowByte & (1 << bit)) msr.lo |= 0x20; // write serialize PCI memory } @@ -505,18 +505,18 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) shadowByte = (uint8_t) (shadowLo >> 24); // load up F000 settings in edx. - for (bit = 8; (bit > 4); bit--) { + for (bit = 7; bit >= 4; bit--) { msr.hi <<= 8; msr.hi |= 1; // cache disable PCI/Shadow memory - if (shadowByte && (1 << bit)) + if (shadowByte & (1 << bit)) msr.hi |= 0x20; // write serialize PCI memory } // load up E000 settings in eax. - for (; bit; bit--) { + for (; bit >= 0; bit--) { msr.lo <<= 8; msr.lo |= 1; // cache disable PCI/Shadow memory - if (shadowByte && (1 << bit)) + if (shadowByte & (1 << bit)) msr.lo |= 0x20; // write serialize PCI memory } |