diff options
| author | Scott Duplichan <scott@notabs.org> | 2011-05-15 22:07:56 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-05-15 22:07:56 +0000 |
| commit | a64ab46b629737658a461914d0d63ae713c0e760 (patch) | |
| tree | 63b05f32b07d0c5759cf04b7c12334dc1d8b7469 | |
| parent | 769527e523bb40ecb33a1f6811dae0d689ca4e26 (diff) | |
| download | coreboot-a64ab46b629737658a461914d0d63ae713c0e760.tar.xz | |
Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/amd/persimmon/devicetree.cb | 14 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/cfg.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/late.c | 14 |
3 files changed, 14 insertions, 18 deletions
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 8ca165b739..3a9ec400a6 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -81,13 +81,13 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end end # f81865f end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 diff --git a/src/southbridge/amd/cimx_wrapper/sb800/cfg.c b/src/southbridge/amd/cimx_wrapper/sb800/cfg.c index 09ff9b6c6c..46ad813499 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/cfg.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/cfg.c @@ -99,10 +99,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->GppFunctionEnable = GPP_CONTROLLER; sb_config->GppLinkConfig = GPP_CFGMODE; //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; - sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED; - sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED; - sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED; - sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED; sb_config->GppUnhidePorts = TRUE; //visable always, even port empty //sb_config->NbSbGen2 = TRUE; //sb_config->GppGen2 = TRUE; diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c index d8816fa1c8..c72b2bec86 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/late.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c @@ -315,7 +315,6 @@ static const struct pci_driver PORTD_driver __pci_driver = { */ static void sb800_enable(device_t dev) { - u8 gpp_port = 0; struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip = (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info); @@ -414,15 +413,16 @@ static void sb800_enable(device_t dev) break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ + sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ + sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ + sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ - gpp_port = (dev->path.pci.devfn) & 0x03; - if (dev->enabled) { - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; - } else { - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; - } + sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; /* * GPP_CFGMODE_X4000: PortA Lanes[3:0] |