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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-11-30 20:37:29 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-03-21 20:12:07 +0100 |
| commit | bb5e77c4787c7bbf079d084087143c5ca85fdcc3 (patch) | |
| tree | ffdf8d9fe89d3ab95e00ea879c2616c0863e5d86 | |
| parent | 70a1dda927951e3d3a163ee899f25420f78b56c1 (diff) | |
| download | coreboot-bb5e77c4787c7bbf079d084087143c5ca85fdcc3.tar.xz | |
nb/x4x: Move checkreset before SPD reading
It makes no sense to read SPDs if the system will reset anyway.
Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17661
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 37 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr2.c | 38 |
2 files changed, 37 insertions, 38 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 639b5b15ab..7d352f11d3 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -302,6 +302,41 @@ static void sdram_detect_ram_speed(struct sysinfo *s) } } +static void checkreset_ddr2(int boot_path) +{ + u8 pmcon2; + u32 pmsts; + + if (boot_path >= 1) { + pmsts = MCHBAR32(PMSTS_MCHBAR); + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + } + + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + + /* do magic 0xf0 thing. */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + + printk(BIOS_DEBUG, "Reset...\n"); + outb(0x6, 0xcf9); + asm ("hlt"); + } + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); +} + /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ @@ -322,6 +357,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map) s.spd_map[2] = spd_map[2]; s.spd_map[3] = spd_map[3]; + checkreset_ddr2(s.boot_path); + /* Detect dimms per channel */ s.dimms_per_ch = 2; reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index e8bb01196e..eca7189145 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -259,41 +259,6 @@ static void clkcross_ddr2(struct sysinfo *s) MCHBAR32(0x70c) = clkxtab[i][j][12]; } -static void checkreset_ddr2(struct sysinfo *s) -{ - u8 pmcon2; - u32 pmsts; - - if (s->boot_path >= 1) { - pmsts = MCHBAR32(PMSTS_MCHBAR); - if (!(pmsts & 1)) - printk(BIOS_DEBUG, - "Channel 0 possibly not in self refresh\n"); - if (!(pmsts & 2)) - printk(BIOS_DEBUG, - "Channel 1 possibly not in self refresh\n"); - } - - pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - - if (pmcon2 & 0x80) { - pmcon2 &= ~0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - - /* do magic 0xf0 thing. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - - printk(BIOS_DEBUG, "Reset...\n"); - outb(0x6, 0xcf9); - asm ("hlt"); - } - pmcon2 |= 0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); -} - static void setioclk_ddr2(struct sysinfo *s) { MCHBAR32(0x1bc) = 0x08060402; @@ -1937,9 +1902,6 @@ void raminit_ddr2(struct sysinfo *s) // Select timings based on SPD info sdram_detect_smallest_params2(s); - // Reset if required - checkreset_ddr2(s); - if (s->boot_path != BOOT_PATH_WARM_RESET) { // Clear self refresh MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) |