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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-02 20:07:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-24 07:43:11 +0000 |
| commit | bc36e298f998f8126837b4ea8e2e56566dc078dc (patch) | |
| tree | af8a3d877a3fcb5c4ab1e8a47727cc2d1aaeb0cf | |
| parent | 1b79b86defc08143c5f6870a40ddbf25b66c0370 (diff) | |
| download | coreboot-bc36e298f998f8126837b4ea8e2e56566dc078dc.tar.xz | |
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add
ELOG wake sources for ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/include/elog.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/skylake/elog.c | 18 |
2 files changed, 28 insertions, 2 deletions
diff --git a/src/include/elog.h b/src/include/elog.h index 0574819e0d..0328a865a4 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -149,6 +149,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b struct elog_event_data_wake { u8 source; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137ec7..795139418d 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -121,7 +121,7 @@ static void pch_log_pme_internal_wake_source(void) #define RP_PME_STS_BIT (1 << 16) static void pch_log_rp_wake_source(void) { - size_t i; + size_t i, maxports; #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; #else @@ -142,9 +142,23 @@ static void pch_log_rp_wake_source(void) { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, }; - for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + + for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev; if (!dev) |