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| author | Iru Cai <mytbk920423@gmail.com> | 2018-12-25 20:35:29 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-11-17 15:10:45 +0800 |
| commit | e03f7363022cd903cf08b2b22cef1dff9464ab2d (patch) | |
| tree | bcde31a6ed9b4365ed8edf2bdc13ac0d3abfae98 | |
| parent | 2355845aa02d1d68fa4e9846ebbe08a15eba459d (diff) | |
| download | coreboot-e03f7363022cd903cf08b2b22cef1dff9464ab2d.tar.xz | |
frag_fffc1c07
| -rw-r--r-- | src/northbridge/intel/haswell/mrc_frag_init_memory.c | 23 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/mrc_init_memory.asm | 25 |
2 files changed, 26 insertions, 22 deletions
diff --git a/src/northbridge/intel/haswell/mrc_frag_init_memory.c b/src/northbridge/intel/haswell/mrc_frag_init_memory.c index 4182b4991d..51d3be241c 100644 --- a/src/northbridge/intel/haswell/mrc_frag_init_memory.c +++ b/src/northbridge/intel/haswell/mrc_frag_init_memory.c @@ -3,6 +3,7 @@ #include "mrc_pei.h" #include <cpu/x86/msr.h> #include "mrc_utils.h" +#include <arch/cpu.h> int frag_fffc1d20(void); int frag_fffc1d20(void) @@ -39,8 +40,7 @@ void *create_raminit_hob(void) return hob; } -void frag_fffc1cd2(void); -void frag_fffc1cd2(void) +static void frag_fffc1cd2(void) { for (int i = 0; i < 0x2ee; i++) { uint8_t tmp = read8((void*)0xfed40000); @@ -112,3 +112,22 @@ int test_memory(void) } return 0; } + +void frag_fffc1c07(void); +int initialize_txt(void); +void frag_fffc1c07() +{ + struct cpuid_result res; + int t; + + res = cpuid_ext(1, 0); + if ((u8)res.ecx & 0x40) { + res = cpuid_ext(1, 0); + t = 0; + if (res.ecx & 0x40) { + t = initialize_txt(); + } + if (t != 1) + frag_fffc1cd2(); + } +} diff --git a/src/northbridge/intel/haswell/mrc_init_memory.asm b/src/northbridge/intel/haswell/mrc_init_memory.asm index 27aa201d14..2704689e9f 100644 --- a/src/northbridge/intel/haswell/mrc_init_memory.asm +++ b/src/northbridge/intel/haswell/mrc_init_memory.asm @@ -74,11 +74,13 @@ extern fcn_fffc83be extern frag_fffc1d20 extern frag_fffc1fc3 extern create_raminit_hob -extern frag_fffc1cd2 +extern frag_fffc1c07 extern set_cpuid extern test_memory +global initialize_txt initialize_txt: +push ebx mov edx, cr4 mov eax, edx or eax, 0x4000 ; cr4 bit 14: Safer Mode Extensions Enable @@ -87,6 +89,7 @@ xor eax, eax mov ebx, eax getsec mov cr4, edx +pop ebx ret @@ -153,27 +156,9 @@ push 0 push gEfiPeiReadOnlyVariablePpiGuid push ecx call dword [eax + 0x20] ; LocatePpi -mov eax, esi -mov ecx, edi -cpuid add esp, 0x20 -and cl, 0x40 -je loc_fffc1d20 ; je 0xfffc1d20 -mov eax, esi -mov ecx, edi -cpuid -mov esi, ecx -xor eax, eax -and esi, 0x40 -je short loc_fffc1ca2 ; je 0xfffc1ca2 -call initialize_txt ; this will set ebx to 0 -xor ebx, ebx - -loc_fffc1ca2: -test al, 1 -je short loc_fffc1d20 -call frag_fffc1cd2 +call frag_fffc1c07 loc_fffc1d20: cmp dword [ebp - 0x509c], 0x11 |