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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-03 21:28:40 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-07 05:41:49 +0000 |
| commit | e119d86ca87937d45e67d00da722c28ac7ceaa9e (patch) | |
| tree | f70f37b4d496c163ecf093c17bd1a8895dc0b41f | |
| parent | d78866399c389ac3195cb7841bac68ae2b22c358 (diff) | |
| download | coreboot-e119d86ca87937d45e67d00da722c28ac7ceaa9e.tar.xz | |
intel/fsp_rangeley: Rename raminit.c to memmap.c
Use a name consistent with the more recent soc/intel.
Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/memmap.c (renamed from src/northbridge/intel/fsp_rangeley/raminit.c) | 0 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index f9bf0507dc..a2f80546d7 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,12 +18,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += raminit.c +ramstage-y += memmap.c ramstage-y += acpi.c ramstage-y += port_access.c -romstage-y += raminit.c +romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/memmap.c index da9ed71a67..da9ed71a67 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/memmap.c |