diff options
| author | Kane Chen <kane.chen@intel.com> | 2018-01-09 09:52:37 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-12 18:18:26 +0000 |
| commit | e13a269f589b0ede64c24bb8cf7644a92d05792a (patch) | |
| tree | ce6bbf41a5328198766ff2a22efbfde3d2eb620e | |
| parent | f40fd5b5087ee8ab43d94c8e51d042095d597276 (diff) | |
| download | coreboot-e13a269f589b0ede64c24bb8cf7644a92d05792a.tar.xz | |
mb/google/fizz: Disable PCH Lan
Fizz has external Lan on PCIE port.
The Lan device on PCH is not used.
BUG=b:70889517
Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 189f49f93f..a3ae44c6b0 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -55,7 +55,7 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "1" + register "EnableLan" = "0" register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" |