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authorArthur Heymans <arthur@aheymans.xyz>2018-07-20 23:31:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-24 18:34:37 +0000
commite750b38e4834867ec362b59f150ef6ae9fe888c6 (patch)
treefa85e7241ca2496c45e103a2a2c62ce053b473cc
parent6b27c38f4afdd7b20100c4a772fa4077ae437cf1 (diff)
downloadcoreboot-e750b38e4834867ec362b59f150ef6ae9fe888c6.tar.xz
cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat
-rw-r--r--src/cpu/intel/haswell/smmrelocate.c4
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c4
-rw-r--r--src/include/cpu/x86/mtrr.h4
-rw-r--r--src/soc/intel/apollolake/cpu.c4
-rw-r--r--src/soc/intel/baytrail/cpu.c4
-rw-r--r--src/soc/intel/braswell/cpu.c4
-rw-r--r--src/soc/intel/broadwell/smmrelocate.c4
-rw-r--r--src/soc/intel/cannonlake/smmrelocate.c4
-rw-r--r--src/soc/intel/denverton_ns/cpu.c4
-rw-r--r--src/soc/intel/fsp_baytrail/cpu.c4
-rw-r--r--src/soc/intel/fsp_broadwell_de/smmrelocate.c4
-rw-r--r--src/soc/intel/skylake/smmrelocate.c4
12 files changed, 24 insertions, 24 deletions
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 9ff1e55c81..56ee47bc97 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -70,8 +70,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_emrr(struct smm_relocation_params *relo_params)
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index e80fa31489..9806882376 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -61,8 +61,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
/* The relocation work is actually performed in SMM context, but the code
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index f52a77b1a7..a4f1f888e3 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -28,8 +28,8 @@
#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
-#define SMRR_PHYS_BASE 0x1f2
-#define SMRR_PHYS_MASK 0x1f3
+#define IA32_SMRR_PHYS_BASE 0x1f2
+#define IA32_SMRR_PHYS_MASK 0x1f3
#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 690589443c..caa3bbf90f 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -223,10 +223,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
+ wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
+ wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase;
}
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 77d2dda8bf..618430b9a8 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -179,10 +179,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
+ wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
+ wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase;
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 31b1b78142..85b04ac81f 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -195,10 +195,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
+ wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
+ wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase;
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 2d90ebce01..08b98e9de1 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -38,8 +38,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_emrr(struct smm_relocation_params *relo_params)
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 3c60ef2b34..e688592a4c 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -41,8 +41,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static void update_save_state(int cpu, uintptr_t curr_smbase,
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index d486435a5b..b7b5550aaa 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -80,10 +80,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
+ wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
+ wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase;
}
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index c7694b9824..a69d046e7b 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -139,10 +139,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
+ wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
+ wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase;
diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index 28bc8c9710..fe7bc6f1ac 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -39,8 +39,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_prmrr(struct smm_relocation_params *relo_params)
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 6a8e64bd42..3db60f9e31 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -41,8 +41,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 10:52:36 +0000