summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorIru Cai <mytbk920423@gmail.com>2018-12-23 23:17:52 +0800
committerIru Cai <mytbk920423@gmail.com>2019-11-17 15:10:44 +0800
commitf910b63f74c59b2b0f967c5d9716e54413941891 (patch)
tree1d06589908332001894e1c17a3c958ac8f0418d7
parent064a5205a3fd05c2912647b674312b95ae38ff8a (diff)
downloadcoreboot-f910b63f74c59b2b0f967c5d9716e54413941891.tar.xz
frag_fffa3eec
-rw-r--r--src/northbridge/intel/haswell/do_raminit_frag.c39
-rw-r--r--src/northbridge/intel/haswell/mrc.asm47
2 files changed, 46 insertions, 40 deletions
diff --git a/src/northbridge/intel/haswell/do_raminit_frag.c b/src/northbridge/intel/haswell/do_raminit_frag.c
index e0d023913c..1cf38e4037 100644
--- a/src/northbridge/intel/haswell/do_raminit_frag.c
+++ b/src/northbridge/intel/haswell/do_raminit_frag.c
@@ -283,3 +283,42 @@ void mrc_set_bars(pei_ram_data *r)
write32((void*)r->mchbar + 0x540c, 0);
}
}
+
+extern EFI_GUID ref_fffcd4a4;
+extern EFI_GUID ref_fffcc8bc;
+void* frag_fffa3eec(void *raminit_ppi);
+void* frag_fffa3eec(void *raminit_ppi)
+{
+ const EFI_PEI_SERVICES **pps = *gpPei;
+ EFI_HOB_DATA *hob;
+
+ (*pps)->CreateHob(pps, 4, 0x6d, (void**)&hob);
+ memcpy((void*)hob + 8, &ref_fffcd4a4, 16);
+ mrc_zeromem((void*)hob + 0x18, 8);
+ mrc_zeromem((void*)hob + 0x20, 8);
+ mrc_zeromem((void*)hob + 0x29, 0x1e);
+ *(uint8_t*)((void*)hob + 0x28) = 0;
+ *(uint8_t*)((void*)hob + 0x6c) = 0;
+
+ if (*(uint8_t*)raminit_ppi > 1) {
+ void *p1 = *(void**)(raminit_ppi + 0xd);
+ *(uint16_t*)((void*)hob + 0x47) = *(uint16_t*)(p1 + 0x4a);
+ *(uint8_t*)((void*)hob + 0x49) = *(uint8_t*)(p1 + 0x49);
+ } else {
+ *(uint16_t*)((void*)hob + 0x47) = 0;
+ *(uint8_t*)((void*)hob + 0x49) = 0;
+ }
+ return hob;
+#if 0
+ void *ppi;
+ (*pps)->LocatePpi(pps, &ref_fffcc8bc, 0, NULL, &ppi);
+
+ *(uint8_t*)((void*)hob + 0x20) = 2;
+ void *p2 = *((void**)(ppi + 1));
+ if (*(uint8_t*)p2 != 0x10) {
+ void *p3 = *((void**)(ppi + 9));
+ void *p4 = *((void**)p3);
+ *(uint8_t*)((void*)hob + 0x21) = *(uint8_t*)(p4 + 0x301);
+ }
+#endif
+}
diff --git a/src/northbridge/intel/haswell/mrc.asm b/src/northbridge/intel/haswell/mrc.asm
index ebc93b27bb..45c66d2cd2 100644
--- a/src/northbridge/intel/haswell/mrc.asm
+++ b/src/northbridge/intel/haswell/mrc.asm
@@ -155,6 +155,8 @@ extern io_fffa4c0d
extern load_usb
extern fill_pei_ram_data
extern mrc_set_bars
+extern frag_fffa3eec
+global ref_fffcc8bc
;; mrc_wdt
@@ -2897,46 +2899,11 @@ add esp, 0xc
loc_fffa3eec:
mov edx, dword [ebp - 0x640]
mov ebx, dword [ebp - 0x628]
-mov esi, ref_fffcd4a4 ; mov esi, 0xfffcd4a4
-mov eax, dword [edx]
-lea edx, [ebp - 0x620]
-push edx
-push 0x6d
-push 4
-push dword [ebp - 0x640]
-call dword [eax + 0x34] ; ucall
-mov eax, dword [ebp - 0x620]
-mov ecx, 4
-mov edx, 8
-lea edi, [eax + 8]
-add eax, 0x18
-rep movsd ; rep movsd dword es:[edi], dword ptr [esi]
-call mrc_zeromem
-mov eax, dword [ebp - 0x620]
-mov edx, 8
-add eax, 0x20
-call mrc_zeromem
-mov eax, dword [ebp - 0x620]
-mov edx, 0x1e
-add eax, 0x29
-call mrc_zeromem
-mov eax, dword [ebp - 0x620]
-add esp, 0x10
-mov byte [eax + 0x28], 0
-mov byte [eax + 0x6c], 0
-cmp byte [ebx], 1
-jbe short loc_fffa3f82 ; jbe 0xfffa3f82
-mov edx, dword [ebx + 0xd]
-mov dx, word [edx + 0x4a]
-mov word [eax + 0x47], dx
-mov edx, dword [ebx + 0xd]
-mov dl, byte [edx + 0x49]
-mov byte [eax + 0x49], dl
-jmp short loc_fffa3f8c ; jmp 0xfffa3f8c
-
-loc_fffa3f82:
-mov word [eax + 0x47], 0
-mov byte [eax + 0x49], 0
+
+push ebx
+call frag_fffa3eec
+mov dword [ebp - 0x620], eax
+pop ebx
loc_fffa3f8c:
mov ecx, dword [ebp - 0x640]