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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-01-10 11:35:24 -0700
committerMarshall Dawson <marshalldawson3rd@gmail.com>2018-01-12 16:00:32 +0000
commit0814b122281d2e4f10e40c2a8d5085f810e2730e (patch)
treee20ce1ca7b9d83571bc13ba2b9d245500e788ed2
parent533ea7adb5d23d32c854f4a3bdbf9c31df7299b4 (diff)
downloadcoreboot-0814b122281d2e4f10e40c2a8d5085f810e2730e.tar.xz
amd/stoneyridge: Keep SPI flash cacheable during POST
A side effect of using the common MTRR assignment code is the flash device loses its WP setting and is no longer cacheable. After MTRR setup, reenable the setting for the duration of POST. TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate() BUG=b:70536683 Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
-rw-r--r--src/soc/amd/stoneyridge/cpu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 0490137988..86429e207e 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -24,6 +24,7 @@
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/smi.h>
+#include <soc/iomap.h>
#include <console/console.h>
/*
@@ -47,6 +48,10 @@ static struct smm_relocation_attrs relo_attrs;
static void pre_mp_init(void)
{
x86_setup_mtrrs_with_detect();
+
+ /* The flash is now no longer cacheable. Reset to WP for performance. */
+ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
x86_mtrr_check();
}