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| author | Nicolas Reinecke <nr@das-labor.org> | 2015-03-29 17:51:11 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-19 21:26:14 +0200 |
| commit | 0b29a7b37c19200516dadc5c4bf0a1eb9d1290ec (patch) | |
| tree | 449bfc1767f9b175ff1483f6a344c2453d2ffa08 | |
| parent | 7effaa4c02d974b59bd86307a54cefb7bb046a3a (diff) | |
| download | coreboot-0b29a7b37c19200516dadc5c4bf0a1eb9d1290ec.tar.xz | |
southbrige/intel/bd82x6x: XHCI replace magic values
Change-Id: I62674ccfb836fb0b02ac562f678cdfa44be98ae3
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9779
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/usb_xhci.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 029da9fb35..7b52ebc3e3 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -448,6 +448,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define USBOCM1 0x35a0 /* 32bit */ #define USBOCM2 0x35a4 /* 32bit */ +/* XHCI USB 3.0 */ +#define XUSB2PRM 0xd4 /* 32bit */ +#define USB3PRM 0xdc /* 32bit */ + /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04 diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index eb89a7d64f..3e6ce6b341 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -38,8 +38,8 @@ static void usb_xhci_init(struct device *dev) reg32 |= 1; pci_write_config32(dev, 0x44, reg32); - pci_write_config32(dev, 0xd4, config->xhci_switchable_ports); - pci_write_config32(dev, 0xdc, config->superspeed_capable_ports); + pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports); + pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports); /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); |