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authorFrans Hendriks <fhendriks@eltan.com>2019-04-05 13:42:14 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-04-11 11:57:55 +0000
commit1385b7dd10385e8ae58b4d988701af1eac060fd3 (patch)
tree63ef17f64c8d495228ec6e4abe30ec9a0fad7de2
parentdd11810367e6a66fb9366d108cb0bb6b1664355a (diff)
downloadcoreboot-1385b7dd10385e8ae58b4d988701af1eac060fd3.tar.xz
drivers/intel/fsp1_1: Configure UART after memory init
FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h2
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c7
2 files changed, 9 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index e266beec60..d608484999 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -91,5 +92,6 @@ void soc_pre_ram_init(struct romstage_params *params);
/* Update the SOC specific memory config param for mma. */
void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
struct mma_config_param *mma_cfg);
+void mainboard_after_memory_init(void);
#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2dd5c77e96..8405c943aa 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -125,6 +125,7 @@ void raminit(struct romstage_params *params)
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
post_code(POST_FSP_MEMORY_INIT);
status = fsp_memory_init(&fsp_memory_init_params);
+ mainboard_after_memory_init();
post_code(0x37);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
@@ -322,3 +323,9 @@ __weak void soc_memory_init_params(
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
+
+/* Initialize the SoC after MemoryInit */
+__weak void mainboard_after_memory_init(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}