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authorSubrata Banik <subrata.banik@intel.com>2019-10-30 17:22:33 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-10-31 15:04:50 +0000
commit154024d2562b3267f3d09c8fe526104cff75d292 (patch)
tree0cf945ccf5e981a8a1c6155303b3f998c05860f5
parent1031aae361511d90954e7072b93c1bdefe28da3e (diff)
downloadcoreboot-154024d2562b3267f3d09c8fe526104cff75d292.tar.xz
soc/intel/{cnl,icl,skl}: Fix multiple whitespace issue
Change-Id: I1e3dc1bd36c5de4e58eef6a3ba8ccbde28fba64b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36465 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/cannonlake/cpu.c2
-rw-r--r--src/soc/intel/icelake/bootblock/pch.c2
-rw-r--r--src/soc/intel/icelake/cpu.c2
-rw-r--r--src/soc/intel/skylake/cpu.c2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a3252c2560..39433a26d9 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -90,7 +90,7 @@ static void soc_config_pwrmbase(void)
/* Enable Bus Master and MMIO Space */
reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MEMORY;
+ reg32 |= PCI_COMMAND_MEMORY;
pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
/* Enable PWRM in PMC */
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index c58b9ad693..7f38279def 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -399,7 +399,7 @@ static void enable_pm_timer_emulation(void)
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
- /* Set PM1 timer IO port and enable*/
+ /* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index aefcaa5a47..e95220b90e 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -72,7 +72,7 @@ static void soc_config_pwrmbase(void)
/* Enable Bus Master and MMIO Space */
reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MEMORY;
+ reg32 |= PCI_COMMAND_MEMORY;
pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
/* Enable PWRM in PMC */
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 0ecccb94e5..a2d9f7a6bc 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -127,7 +127,7 @@ static void enable_pm_timer_emulation(void)
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
- /* Set PM1 timer IO port and enable*/
+ /* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 63142b9b3f..3ac14514bb 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -414,7 +414,7 @@ static void enable_pm_timer_emulation(void)
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
- /* Set PM1 timer IO port and enable*/
+ /* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);