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authorMartin Roth <martinroth@google.com>2016-11-28 14:30:38 -0700
committerMartin Roth <martinroth@google.com>2016-11-30 00:21:53 +0100
commit19424a157df596b814a7c95bac219b1f95fe04ff (patch)
tree9d657142afdcb60e637d33f8d14db5c7eaec7204
parent46fef017227c8695c988188976d17935809bcc73 (diff)
downloadcoreboot-19424a157df596b814a7c95bac219b1f95fe04ff.tar.xz
mb/google/oak: replace symbolic links
These three files were added as symbolic links to the other files in the same directory. Delete the links, and copy the real files into their places. Because of the varied environments that coreboot is built in, we don't want to have symbolic links in the tree. These three files were the only cases of symbolic links. Change-Id: If69f40c2c4cdcabc4fdfc1d6026a91c0791756da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--[l---------]src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E324EB-2GB.inc117
-rw-r--r--[l---------]src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc117
-rw-r--r--[l---------]src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc117
3 files changed, 348 insertions, 3 deletions
diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E324EB-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E324EB-2GB.inc
index 1ba33c73a7..578343b7c0 120000..100644
--- a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E324EB-2GB.inc
+++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E324EB-2GB.inc
@@ -1 +1,116 @@
-sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc \ No newline at end of file
+{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
+ {
+ .impedance_drvp = 0x9,
+ .impedance_drvn = 0xa,
+ .datlat_ucfirst = 19,
+
+ .ca_train = {
+ [CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
+ [CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
+ },
+
+ .ca_train_center = {
+ [CHANNEL_A] = 2,
+ [CHANNEL_B] = 0
+ },
+
+ .wr_level = {
+ [CHANNEL_A] = { 5, 6, 5, 6},
+ [CHANNEL_B] = { 6, 6, 6, 4}
+ },
+
+ .gating_win = {
+ [CHANNEL_A] = {
+ { 28, 64},
+ { 0, 0}
+ },
+ [CHANNEL_B] = {
+ { 28, 64},
+ { 0, 0}
+ }
+ },
+
+ .rx_dqs_dly = {
+ [CHANNEL_A] = 0x110e0b0b,
+ [CHANNEL_B] = 0x12100d0d
+ },
+
+ .rx_dq_dly = {
+ [CHANNEL_A] = {
+ 0x01040302,
+ 0x04010300,
+ 0x02040300,
+ 0x04030302,
+ 0x04070400,
+ 0x07070707,
+ 0x05070808,
+ 0x00010404
+ },
+ [CHANNEL_B] = {
+ 0x05060604,
+ 0x04010400,
+ 0x05070300,
+ 0x05030504,
+ 0x07090500,
+ 0x08090707,
+ 0x080a0a0a,
+ 0x02000604
+ }
+ },
+ },
+ {
+ .actim = 0xaafd478c,
+ .actim1 = 0x91001f59,
+ .actim05t = 0x000025e1,
+ .conf1 = 0x00048403,
+ .conf2 = 0x030000a9,
+ .ddr2ctl = 0x000063b1,
+ .gddr3ctl1 = 0x11000000,
+ .misctl0 = 0x21000000,
+ .pd_ctrl = 0xd1976442,
+ .rkcfg = 0x002156c0,
+ .test2_3 = 0xbfc70401,
+ .test2_4 = 0x2801110d
+ },
+ {
+ .cona = 0x20102017,
+ .conb = 0x17283544,
+ .conc = 0x0a1a0b1a,
+ .cond = 0x00000000,
+ .cone = 0xffff0848,
+ .conf = 0x08420000,
+ .cong = 0x2b2b2a38,
+ .conh = 0x00000000,
+ .conm_1 = 0x40000500,
+ .conm_2 = 0x400005ff,
+ .mdct_1 = 0x80030303,
+ .mdct_2 = 0x34220c3f,
+ .test0 = 0xcccccccc,
+ .test1 = 0xcccccccc,
+ .testb = 0x00060124,
+ .testc = 0x38470000,
+ .testd = 0x00000000,
+ .arba = 0x7f077a49,
+ .arbc = 0xa0a070dd,
+ .arbd = 0x07007046,
+ .arbe = 0x40407046,
+ .arbf = 0xa0a070c6,
+ .arbg = 0xffff7047,
+ .arbi = 0x20406188,
+ .arbj = 0x9719595e,
+ .arbk = 0x64f3fc79,
+ .slct_1 = 0x00010800,
+ .slct_2 = 0xff03ff00,
+ .bmen = 0x00ff0001
+ },
+ {
+ .mrs_1 = 0x00830001,
+ .mrs_2 = 0x001c0002,
+ .mrs_3 = 0x00010003,
+ .mrs_10 = 0x00ff000a,
+ .mrs_11 = 0x0000000b,
+ .mrs_63 = 0x0000003f
+ },
+ .type = TYPE_LPDDR3,
+ .dram_freq = 896 * MHz,
+},
diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc
index 1ba33c73a7..578343b7c0 120000..100644
--- a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc
+++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc
@@ -1 +1,116 @@
-sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc \ No newline at end of file
+{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
+ {
+ .impedance_drvp = 0x9,
+ .impedance_drvn = 0xa,
+ .datlat_ucfirst = 19,
+
+ .ca_train = {
+ [CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
+ [CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
+ },
+
+ .ca_train_center = {
+ [CHANNEL_A] = 2,
+ [CHANNEL_B] = 0
+ },
+
+ .wr_level = {
+ [CHANNEL_A] = { 5, 6, 5, 6},
+ [CHANNEL_B] = { 6, 6, 6, 4}
+ },
+
+ .gating_win = {
+ [CHANNEL_A] = {
+ { 28, 64},
+ { 0, 0}
+ },
+ [CHANNEL_B] = {
+ { 28, 64},
+ { 0, 0}
+ }
+ },
+
+ .rx_dqs_dly = {
+ [CHANNEL_A] = 0x110e0b0b,
+ [CHANNEL_B] = 0x12100d0d
+ },
+
+ .rx_dq_dly = {
+ [CHANNEL_A] = {
+ 0x01040302,
+ 0x04010300,
+ 0x02040300,
+ 0x04030302,
+ 0x04070400,
+ 0x07070707,
+ 0x05070808,
+ 0x00010404
+ },
+ [CHANNEL_B] = {
+ 0x05060604,
+ 0x04010400,
+ 0x05070300,
+ 0x05030504,
+ 0x07090500,
+ 0x08090707,
+ 0x080a0a0a,
+ 0x02000604
+ }
+ },
+ },
+ {
+ .actim = 0xaafd478c,
+ .actim1 = 0x91001f59,
+ .actim05t = 0x000025e1,
+ .conf1 = 0x00048403,
+ .conf2 = 0x030000a9,
+ .ddr2ctl = 0x000063b1,
+ .gddr3ctl1 = 0x11000000,
+ .misctl0 = 0x21000000,
+ .pd_ctrl = 0xd1976442,
+ .rkcfg = 0x002156c0,
+ .test2_3 = 0xbfc70401,
+ .test2_4 = 0x2801110d
+ },
+ {
+ .cona = 0x20102017,
+ .conb = 0x17283544,
+ .conc = 0x0a1a0b1a,
+ .cond = 0x00000000,
+ .cone = 0xffff0848,
+ .conf = 0x08420000,
+ .cong = 0x2b2b2a38,
+ .conh = 0x00000000,
+ .conm_1 = 0x40000500,
+ .conm_2 = 0x400005ff,
+ .mdct_1 = 0x80030303,
+ .mdct_2 = 0x34220c3f,
+ .test0 = 0xcccccccc,
+ .test1 = 0xcccccccc,
+ .testb = 0x00060124,
+ .testc = 0x38470000,
+ .testd = 0x00000000,
+ .arba = 0x7f077a49,
+ .arbc = 0xa0a070dd,
+ .arbd = 0x07007046,
+ .arbe = 0x40407046,
+ .arbf = 0xa0a070c6,
+ .arbg = 0xffff7047,
+ .arbi = 0x20406188,
+ .arbj = 0x9719595e,
+ .arbk = 0x64f3fc79,
+ .slct_1 = 0x00010800,
+ .slct_2 = 0xff03ff00,
+ .bmen = 0x00ff0001
+ },
+ {
+ .mrs_1 = 0x00830001,
+ .mrs_2 = 0x001c0002,
+ .mrs_3 = 0x00010003,
+ .mrs_10 = 0x00ff000a,
+ .mrs_11 = 0x0000000b,
+ .mrs_63 = 0x0000003f
+ },
+ .type = TYPE_LPDDR3,
+ .dram_freq = 896 * MHz,
+},
diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc
index 564af33992..f03f858b82 120000..100644
--- a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc
+++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc
@@ -1 +1,116 @@
-sdram-lpddr3-K4E6E304EB-4GB.inc \ No newline at end of file
+{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */
+ {
+ .impedance_drvp = 0xc,
+ .impedance_drvn = 0xd,
+ .datlat_ucfirst = 19,
+
+ .ca_train = {
+ [CHANNEL_A] = { 8, 7, 6, 7, 4, 2, 2, 3, 4, 5},
+ [CHANNEL_B] = { 0, 0, 1, 0, 0, 5, 5, 3, 6, 5}
+ },
+
+ .ca_train_center = {
+ [CHANNEL_A] = 2,
+ [CHANNEL_B] = 0
+ },
+
+ .wr_level = {
+ [CHANNEL_A] = { 5, 6, 5, 6},
+ [CHANNEL_B] = { 6, 6, 6, 4}
+ },
+
+ .gating_win = {
+ [CHANNEL_A] = {
+ { 28, 64},
+ { 28, 64}
+ },
+ [CHANNEL_B] = {
+ { 28, 64},
+ { 28, 64}
+ }
+ },
+
+ .rx_dqs_dly = {
+ [CHANNEL_A] = 0x110e0b0b,
+ [CHANNEL_B] = 0x12100d0d
+ },
+
+ .rx_dq_dly = {
+ [CHANNEL_A] = {
+ 0x01040302,
+ 0x04010300,
+ 0x02040300,
+ 0x04030302,
+ 0x04070400,
+ 0x07070707,
+ 0x05070808,
+ 0x00010404
+ },
+ [CHANNEL_B] = {
+ 0x05060604,
+ 0x04010400,
+ 0x05070300,
+ 0x05030504,
+ 0x07090500,
+ 0x08090707,
+ 0x080a0a0a,
+ 0x02000604
+ }
+ },
+ },
+ {
+ .actim = 0xaafd478c,
+ .actim1 = 0x91001f59,
+ .actim05t = 0x000025e1,
+ .conf1 = 0x00048403,
+ .conf2 = 0x030000a9,
+ .ddr2ctl = 0x000063b1,
+ .gddr3ctl1 = 0x11000000,
+ .misctl0 = 0x21000000,
+ .pd_ctrl = 0xd1976442,
+ .rkcfg = 0x002156c1,
+ .test2_3 = 0xbfc70401,
+ .test2_4 = 0x2801110d
+ },
+ {
+ .cona = 0xa053a057,
+ .conb = 0x17283544,
+ .conc = 0x0a1a0b1a,
+ .cond = 0x00000000,
+ .cone = 0xffff0848,
+ .conf = 0x08420000,
+ .cong = 0x2b2b2a38,
+ .conh = 0x00000000,
+ .conm_1 = 0x40000500,
+ .conm_2 = 0x400005ff,
+ .mdct_1 = 0x80030303,
+ .mdct_2 = 0x34220c3f,
+ .test0 = 0xcccccccc,
+ .test1 = 0xcccccccc,
+ .testb = 0x00060124,
+ .testc = 0x38470000,
+ .testd = 0x00000000,
+ .arba = 0x7f077a49,
+ .arbc = 0xa0a070dd,
+ .arbd = 0x07007046,
+ .arbe = 0x40407046,
+ .arbf = 0xa0a070c6,
+ .arbg = 0xffff7047,
+ .arbi = 0x20406188,
+ .arbj = 0x9719595e,
+ .arbk = 0x64f3fc79,
+ .slct_1 = 0x00010800,
+ .slct_2 = 0xff03ff00,
+ .bmen = 0x00ff0001
+ },
+ {
+ .mrs_1 = 0x00830001,
+ .mrs_2 = 0x001c0002,
+ .mrs_3 = 0x00010003,
+ .mrs_10 = 0x00ff000a,
+ .mrs_11 = 0x0000000b,
+ .mrs_63 = 0x0000003f
+ },
+ .type = TYPE_LPDDR3,
+ .dram_freq = 896 * MHz,
+},