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authorStefan Reinauer <stepan@coresystems.de>2010-04-13 21:31:42 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-13 21:31:42 +0000
commit1abf46c74ed34eb394921d2f72817c728e3bb9ee (patch)
treeb94d67e90890839332d31487aa7ee0cae0d7f26c
parent5ae1db0a9b3904c27c9d180170be844ee39ee869 (diff)
downloadcoreboot-1abf46c74ed34eb394921d2f72817c728e3bb9ee.tar.xz
ip1000: fix seabios start, fix flash gpio detection
simplify i82830 code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/thomson/ip1000/mainboard.c23
-rw-r--r--src/northbridge/intel/i82830/northbridge.c83
2 files changed, 48 insertions, 58 deletions
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index eeac3e3fc9..e8b87baa88 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -74,27 +74,15 @@ static void parport_gpios(void)
static void flash_gpios(void)
{
- u32 flash_base = 0xfff80000;
- u8 manufacturer_id, device_id;
-
- // reset mode
- write8(flash_base, 0xff);
- udelay(10);
- // read id
- write8(flash_base, 0x90);
- udelay(10);
- manufacturer_id = read8(flash_base);
- device_id = read8(flash_base + 1);
- // reset mode
- write8(flash_base, 0xff);
- udelay(10);
+ u8 manufacturer_id = read8(0xffbc0000);
+ u8 device_id = read8(0xffbc0001);
if ((manufacturer_id == 0x20) &&
((device_id == 0x2c) || (device_id == 0x2d))) {
printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
(device_id==0x2c)?'4':'8');
u8 fgpi = read8(0xffbc0100);
- printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]",
+ printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
(fgpi & (1 << 0)) ? 'X' : ' ',
(fgpi & (1 << 1)) ? 'X' : ' ',
(fgpi & (1 << 2)) ? 'X' : ' ',
@@ -109,7 +97,6 @@ static void flash_gpios(void)
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
{
- u8 display_id;
#define BOOT_DISPLAY_DEFAULT 0
#define BOOT_DISPLAY_CRT (1 << 0)
#define BOOT_DISPLAY_TV (1 << 1)
@@ -126,8 +113,8 @@ static int int15_handler(void)
switch (M.x86.R_AX) {
case 0x5f35: /* Boot Display */
M.x86.R_AX = 0x005f; // Success
- // M.x86.R_CL = BOOT_DISPLAY_TV;
- M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+ M.x86.R_CL = BOOT_DISPLAY_TV2;
+ //M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
break;
case 0x5f36: /* Boot TV Format Hook */
printk(BIOS_DEBUG, "Boot TV Format Hook. TODO\n");
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index 5cd13b7033..aff13838d4 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -114,49 +114,52 @@ static void pci_domain_set_resources(device_t dev)
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
- if (mc_dev) {
- unsigned long tomk, tolmk;
- int idx;
-
- if (CONFIG_VIDEO_MB == 512) {
- igd_memory = (CONFIG_VIDEO_MB);
- printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
- } else {
- igd_memory = (CONFIG_VIDEO_MB * 1024);
- printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
- }
-
- /* Get the value of the highest DRB. This tells the end of
- * the physical memory. The units are ticks of 32MB
- * i.e. 1 means 32MB.
- */
- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
- tomk -= igd_memory;
-
- /* For reserving UMA memory in the memory map */
- uma_memory_base = tomk * 1024ULL;
- uma_memory_size = igd_memory * 1024ULL;
- printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
-
- /* Compute the top of low memory. */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory. */
- tolmk = tomk;
- }
-
- /* Report the memory regions. */
- idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 1024, tolmk - 1024);
+ if (!mc_dev)
+ return;
-#if CONFIG_WRITE_HIGH_TABLES==1
- /* Leave some space for ACPI, PIRQ and MP tables */
- high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
- high_tables_size = HIGH_TABLES_SIZE * 1024;
-#endif
+ unsigned long tomk, tolmk;
+ int idx;
+
+ if (CONFIG_VIDEO_MB == 512) {
+ igd_memory = (CONFIG_VIDEO_MB);
+ printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
+ } else {
+ igd_memory = (CONFIG_VIDEO_MB * 1024);
+ printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
+ }
+
+ /* Get the value of the highest DRB. This tells the end of
+ * the physical memory. The units are ticks of 32MB
+ * i.e. 1 means 32MB.
+ */
+ tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
+ tomk -= igd_memory;
+
+ /* For reserving UMA memory in the memory map */
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size = igd_memory * 1024ULL;
+ printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
+
+ /* Compute the top of low memory. */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory. */
+ tolmk = tomk;
}
+
+ /* Report the memory regions. */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 768, 256);
+ ram_resource(dev, idx++, 1024, tolmk - 1024);
+
assign_resources(&dev->link[0]);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
static struct device_operations pci_domain_ops = {