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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-20 00:01:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-24 07:42:08 +0000 |
| commit | 1b79b86defc08143c5f6870a40ddbf25b66c0370 (patch) | |
| tree | cec167c81e5e8835aec25694e7cda3fbaa5849c0 | |
| parent | 7398c95d9c3a56d16e2c8f6c6f5e0fabec6ca6bf (diff) | |
| download | coreboot-1b79b86defc08143c5f6870a40ddbf25b66c0370.tar.xz | |
mb/supermicro/x11-lga1151-series: enable SLP_S0 as vendor does
This enables SLP_S0 for x11 boards.
Change-Id: I7240ed631bf72b1d3c9ea887da43772781c80b45
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b94bee8d90..1b9dc271b6 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -92,7 +92,8 @@ chip soc/intel/skylake # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |