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authorArthur Heymans <arthur@aheymans.xyz>2017-01-19 16:45:45 +0100
committerNico Huber <nico.h@gmx.de>2017-01-20 23:41:10 +0100
commit1f060287934219a3b3b7ec0f41d4533e2c450a00 (patch)
tree51f953121f443c6b2eafb6f2d45e71514fb8a0a9
parent23bb036dcb76c30efa708f09a96184583cc367d1 (diff)
downloadcoreboot-1f060287934219a3b3b7ec0f41d4533e2c450a00.tar.xz
nb/gm45/gma.c: Fix reported Pixel clock
Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18180 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/northbridge/intel/gm45/gma.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 4886bb27c8..cbb845171e 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -203,8 +203,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1);
printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
- BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) /
- (pixel_n + 2) / (pixel_p1 * pixel_p2)));
+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
+ (pixel_n + 2) / (pixel_p1 * pixel_p2));
write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21)
@@ -479,8 +479,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);
printk(BIOS_SPEW, "Pixel clock %d kHz\n",
- BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) /
- (pixel_n + 2) / (pixel_p1 * pixel_p2)));
+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
+ (pixel_n + 2) / (pixel_p1 * pixel_p2));
mdelay(1);
write32(mmio + FP0(0), (pixel_n << 16)