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| author | Philipp Hug <philipp@hug.cx> | 2018-07-07 13:34:28 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-14 14:34:09 +0000 |
| commit | 26036d9db342ccee13b8dfaab9aefa9956a067f1 (patch) | |
| tree | bd6f203e83dffda6da56ef8f970274d41109e78d | |
| parent | 2326a284ac6a6646a918331425952ece2da723c1 (diff) | |
| download | coreboot-26036d9db342ccee13b8dfaab9aefa9956a067f1.tar.xz | |
arch/riscv: Only execute on hart 0 for now
Only execute coreboot on hart 0 until synchronisation between hart's is ready.
Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/arch/riscv/bootblock.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 81a4455d97..95e1923ce2 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -24,6 +24,12 @@ .global _estack .globl _start _start: + csrr a0, mhartid + li a3, 0 + beq a0, a3, _hart_zero +_hart_loop: + j _hart_loop +_hart_zero: # The boot ROM may pass the following arguments to coreboot: # a0: the value of mhartid |