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authorPeichao Wang <peichao.wang@bitland.corp-partner.google.com>2019-08-27 16:51:04 +0800
committerMartin Roth <martinroth@google.com>2019-09-04 22:01:37 +0000
commit28086f0d2c6b8a321087d6bd201e8caa72996522 (patch)
tree4329759176867d9c9f1eeaae2882af3fb072afc2
parent4510a8f4b37418eeb7f71fa47ffb1e03a9920457 (diff)
downloadcoreboot-28086f0d2c6b8a321087d6bd201e8caa72996522.tar.xz
mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T table
Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/mainboard/google/kahlee/OemCustomize.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 886e14f265..8e5d8eb5b1 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -39,7 +39,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
PSO_END
};
/* Liara-specific 2T memory configuration */
-static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
+static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
@@ -58,9 +58,9 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if (CONFIG(BOARD_GOOGLE_LIARA))
+ if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA))
PostParams->MemConfig.PlatformMemoryConfiguration =
- (PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
+ (PSO_ENTRY *)DDR4_2T_MemoryConfiguration;
else
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;