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authorAndrey Petrov <anpetrov@fb.com>2020-04-20 23:00:54 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-04-24 19:42:57 +0000
commit2f96970e1f4e586a4c5928fefab1bc0f98bc1351 (patch)
treeb5555adffe4d96859ebfea334c1a5cd4cb0f74ab
parent6d9dc243c76dfeef7b5b15e421f4a36e0247faea (diff)
downloadcoreboot-2f96970e1f4e586a4c5928fefab1bc0f98bc1351.tar.xz
mb/intel/cedarisland_crb: Add dummy mainboard_memory_init_params()
Add a dummy implementation (currently FSP defaults are meant for CRB). It is needed only to prevent build breakage. Change-Id: I67b1a693886a29bdaf23f1f3f249da52ba65451a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
-rw-r--r--src/mainboard/intel/cedarisland_crb/Makefile.inc1
-rw-r--r--src/mainboard/intel/cedarisland_crb/romstage.c8
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/Makefile.inc b/src/mainboard/intel/cedarisland_crb/Makefile.inc
index 8501868fbf..9bd017393c 100644
--- a/src/mainboard/intel/cedarisland_crb/Makefile.inc
+++ b/src/mainboard/intel/cedarisland_crb/Makefile.inc
@@ -1 +1,2 @@
bootblock-y += bootblock.c
+romstage-y += romstage.c
diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c
new file mode 100644
index 0000000000..94af1b6dfe
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/romstage.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+}