diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-04-23 22:13:07 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-25 15:54:24 +0000 |
| commit | 358ec83d03d67a0215c6cad7c18f2119b55dc8c2 (patch) | |
| tree | 3b5cdbf63c93c91fd9074fb887ba7667ebd682b5 | |
| parent | 0f49dd26ad5ee726d5d36c9eefaff72494d0bb3a (diff) | |
| download | coreboot-358ec83d03d67a0215c6cad7c18f2119b55dc8c2.tar.xz | |
northbridge/via/vx900: Remove unused variables
The `printram` function only expands to a value only in debug builds.
This isn't done in default builds.
Change-Id: Ic88c4cc730ae2d0d0718c7f71260cd2b45a3ddcd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/northbridge/via/vx900/raminit_ddr3.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index e03470c704..4f79ed35b0 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -554,7 +554,6 @@ static u8 vx900_get_CWL(u8 CAS) static void vx900_dram_timing(ramctr_timing * ctrl) { u8 reg8, val, tFAW, tRRD; - u32 val32; /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066) so make sure * we cap it if we have faster DIMMs. @@ -569,8 +568,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl) ctrl->tCK = TCK_266MHZ; } - val32 = (1000 << 8) / ctrl->tCK; - printram("Selected DRAM frequency: %u MHz\n", val32); + printram("Selected DRAM frequency: %u MHz\n", (1000 << 8) / ctrl->tCK); /* Find CAS and CWL latencies */ val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |