summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@google.com>2014-10-30 11:53:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2014-12-05 09:20:41 +0100
commit3cf6aea871e4b5929959124356a7775ff21d65ac (patch)
tree2b162d608dc0ebb6b102bda94d474d11666f7c15
parentc3d49984f6fadbc82bc607851e3236191fe551fd (diff)
downloadcoreboot-3cf6aea871e4b5929959124356a7775ff21d65ac.tar.xz
x86: Update the check for Forbidden global variables
Add a section .illegal_globals to romstage and check that the section does not contain any variables while creating romstage. [pg: Handle individual AGESA special cases in the linker script instead of whitelisting everything remotely AGESA related in the Makefile.] Change-Id: I866681f51a44bc21770d32995c281b556a90c153 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7306 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/arch/x86/Makefile.inc5
-rw-r--r--src/arch/x86/init/romstage.ld15
2 files changed, 18 insertions, 2 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9e67459949..a92c55c423 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -206,9 +206,10 @@ romstage-libs ?=
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(romstage-objs) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld
- $(NM_romstage) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \
+ $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders && \
+ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \
echo "Forbidden global variables in romstage:"; \
- $(NM_romstage) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \
+ $(NM_romstage) $(objcbfs)/romstage_null.offenders; false; \
else true; fi
$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs)
diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld
index d6eb5111ef..99bcc8e748 100644
--- a/src/arch/x86/init/romstage.ld
+++ b/src/arch/x86/init/romstage.ld
@@ -65,5 +65,20 @@ SECTIONS
preram_cbmem_console = .;
}
+ /* Global variables are not allowed in romstage
+ * This section is checked during stage creation to ensure
+ * that there are no global variables present
+ */
+
+ . = 0xffffff00;
+ .illegal_globals . : {
+ *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data)
+ *(.data.*)
+ *(.bss)
+ *(.bss.*)
+ *(.sbss)
+ *(.sbss.*)
+ }
+
_bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
}