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authorShamile Khan <shamile.khan@intel.com>2018-03-21 14:43:42 -0700
committerFurquan Shaikh <furquan@google.com>2018-03-23 01:23:20 +0000
commit3d9462a07f0250cf628b7874620f9f682b7a020e (patch)
tree955d4dd628b0ab3537d00f180b7cc50c6bdd1168
parent5b2a4b4087dd98c9c7e5e1dc4fc849fb44b7ed07 (diff)
downloadcoreboot-3d9462a07f0250cf628b7874620f9f682b7a020e.tar.xz
soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal.
BUG=b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I1858c7843d16b6b63fc30762a889916bbb9b781a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25311 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/apollolake/romstage.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 1db2982214..a8a0dd1d44 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -304,6 +304,17 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
die("Can not find SoC devicetree\n");
m_cfg->PrmrrSize = config->PrmrrSize;
+
+ /* FSP performs a PERST# signal deassertion for PCIe ports with
+ * the GPIO address specified in these UPDs. Over-ride the default
+ * addresses with 0 to bypass PERST# signal deassertion in FSP.
+ */
+ m_cfg->RootPort0Perst = 0;
+ m_cfg->RootPort1Perst = 0;
+ m_cfg->RootPort2Perst = 0;
+ m_cfg->RootPort3Perst = 0;
+ m_cfg->RootPort4Perst = 0;
+ m_cfg->RootPort5Perst = 0;
#endif
}