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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-04-29 16:25:01 +0800
committerDuncan Laurie <dlaurie@chromium.org>2019-05-01 20:07:48 +0000
commit43a3c513f85b5af8958da253aa5ca377a4470ab3 (patch)
treef80b7b30b23280fd44d7ecea9cb3ad463c1f2401
parent7144702f8340ff09d85c0a780b71f94dfac5d7ea (diff)
downloadcoreboot-43a3c513f85b5af8958da253aa5ca377a4470ab3.tar.xz
mb/google/sarien: Disable S5 wake on LAN by default
Chromebook doesn't require support wake on LAN in S5. Disable it by default for power saving. BUG=b:131571666 TEST= check LAN indicator is off under S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb3
-rw-r--r--src/soc/intel/cannonlake/chip.h4
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c4
3 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 7dd9f154ef..e9786f14eb 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -53,6 +53,9 @@ chip soc/intel/cannonlake
# Enable DDC for DDI port B
register "DdiPortBDdc" = "1"
+ register "LanWakeFromDeepSx" = "0"
+ register "WolEnableOverride" = "0"
+
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9bba226e58..40d9f71eed 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -400,6 +400,10 @@ struct soc_intel_cannonlake_config {
/* Unlock all GPIO Pads */
uint8_t PchUnlockGpioPads;
+
+ /* Enable GBE wakeup */
+ uint8_t LanWakeFromDeepSx;
+ uint8_t WolEnableOverride;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 61d2520693..cc01d10fe8 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -212,6 +212,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->DdiPortDDdc = config->DdiPortDDdc;
params->DdiPortFDdc = config->DdiPortFDdc;
+ /* WOL */
+ params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
+ params->PchPmWolEnableOverride = config->WolEnableOverride;
+
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;