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authorAaron Durbin <adurbin@chromium.org>2013-10-29 17:00:07 -0500
committerAaron Durbin <adurbin@google.com>2014-02-27 06:13:16 +0100
commit4477050e223450e42f7b55bdef10153004c216d6 (patch)
tree974145d0a0f38cf80e64ebea3d49590ce59f7bc5
parentd7bc23ac8e034de2bf33c50a1f209d7d23250e6b (diff)
downloadcoreboot-4477050e223450e42f7b55bdef10153004c216d6.tar.xz
rambi: add all on-board devices
Add the on-board devices in the SoC to the device tree. Also, disable the unused devices aside from TXE and HDA. Those particular devices cause the system to shut down when they are disabled. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Noted the calls to the southcluster disable function. Change-Id: I482c1c9609833054aeb2948144af54b57d3df086 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174645 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4912 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
-rw-r--r--src/mainboard/google/rambi/devicetree.cb34
1 files changed, 31 insertions, 3 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index c6ea97cb76..3086ebf4e8 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -3,8 +3,36 @@ chip soc/intel/baytrail
device lapic 0 on end
end
device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 1f.0 on end # LPC Bridge
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 on end # HSUART2
+ device pci 1e.5 on end # SPI
+ device pci 1f.0 on end # LPC Bridge
+ device pci 1f.3 off end # SMBus
end
end