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| author | Jes Klinke <jbk@google.com> | 2020-08-28 13:44:21 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-02 10:37:20 +0000 |
| commit | 476ca3a0b6b6a9160a4c30576bfcac899d4ceae4 (patch) | |
| tree | e3f123524f1a00e477a97944df8586bbb0f20271 | |
| parent | 2ad859988b5243411393fdf3116eea281b92b1bb (diff) | |
| download | coreboot-476ca3a0b6b6a9160a4c30576bfcac899d4ceae4.tar.xz | |
soc/intel/tigerlake: Add mainboard hook for overriding SoC config
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137
Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/ramstage.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 0a5fbe71e0..1601c2c58d 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -82,6 +82,11 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_UART2 }; +__weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) +{ + /* Override settings per board. */ +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -92,6 +97,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) struct device *dev; struct soc_intel_tigerlake_config *config; config = config_of_soc(); + mainboard_update_soc_chip_config(config); /* Parse device tree and enable/disable Serial I/O devices */ parse_devicetree(params); diff --git a/src/soc/intel/tigerlake/include/soc/ramstage.h b/src/soc/intel/tigerlake/include/soc/ramstage.h index 8188fbdb84..ec64eec46f 100644 --- a/src/soc/intel/tigerlake/include/soc/ramstage.h +++ b/src/soc/intel/tigerlake/include/soc/ramstage.h @@ -9,6 +9,7 @@ #include <soc/soc_chip.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config); void soc_init_pre_device(void *chip_info); #endif |