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authorFelix Held <felix-coreboot@felixheld.de>2020-07-15 22:22:10 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-07-16 23:38:44 +0000
commit4794264ff1089bdb45c6bbc88fc29300ccdb314d (patch)
treea20ed6fe26e472d88f3dbd805990d294fce80092
parentb39e10dbaa4024560b5faa90ad8ef14135d51d69 (diff)
downloadcoreboot-4794264ff1089bdb45c6bbc88fc29300ccdb314d.tar.xz
mb/amd/mandolin: fix DXIO lane numbers
The DXIO descriptors use the logical and not the physical lane numbers, which are different. Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
index d8969b2a66..87cb6b6d91 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
+++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
@@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WWAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 2,
- .end_lane = 2,
+ .start_lane = 6,
+ .end_lane = 6,
.device_number = 1,
.function_number = 4,
.link_aspm = ASPM_L1,
@@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WIFI */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 3,
- .end_lane = 3,
+ .start_lane = 7,
+ .end_lane = 7,
.gpio_group_id = 1,
.device_number = 1,
.function_number = 5,
@@ -87,8 +87,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* SATA EXPRESS */
.port_present = true,
.engine_type = SATA_ENGINE,
- .start_lane = 6,
- .end_lane = 7,
+ .start_lane = 2,
+ .end_lane = 3,
.gpio_group_id = 1,
.channel_type = SATA_CHANNEL_LONG,
}