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authorArthur Heymans <arthur@aheymans.xyz>2018-11-19 13:08:01 +0100
committerFelix Held <felix-coreboot@felixheld.de>2018-11-25 16:44:28 +0000
commit48fa9225ca18e6320e032b8eedf81087de224cc4 (patch)
treeef52a6b19b084e08f0cae184ddcf68b7d91a0f0a
parent9651058c42e69e00e47ccbcdbbc6b4e5ab7b4a63 (diff)
downloadcoreboot-48fa9225ca18e6320e032b8eedf81087de224cc4.tar.xz
nb/intel/gm45/northbridge.c: Check for NULL pointers
Change-Id: Ic12a8c145d6348086f9931af93ce6d3b3dcb9039 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/northbridge/intel/gm45/northbridge.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index a738905ceb..0fd7fe5a92 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -228,14 +228,23 @@ u32 northbridge_get_tseg_base(void)
u32 northbridge_get_tseg_size(void)
{
- const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),
- D0F0_ESMRAMC);
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ if (dev == NULL)
+ die("could not find pci 00:00.0!\n");
+
+ const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
return decode_tseg_size(esmramc) << 10;
}
void northbridge_write_smram(u8 smram)
{
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_SMRAM, smram);
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ if (dev == NULL)
+ die("could not find pci 00:00.0!\n");
+
+ pci_write_config8(dev, D0F0_SMRAM, smram);
}
/*