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authorMatt Delco <delco@chromium.org>2018-08-13 13:42:05 -0700
committerDuncan Laurie <dlaurie@chromium.org>2018-08-17 20:13:21 +0000
commit4988fe2986078a8d8f87f5683ee3c820655895ca (patch)
treee6c337d1a2a6827adbfec666e161ba7d8e0f5bfe
parentb425bc8cd062ac2a8c01e6ce79b88d1ba9729f7d (diff)
downloadcoreboot-4988fe2986078a8d8f87f5683ee3c820655895ca.tar.xz
src/include: add more msr defines
This change adds some MSRs that are needed in a subsequent change to add support for Continuous Performance Control. Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/include/cpu/x86/msr.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index c2e99446e5..74c2521af5 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -11,7 +11,13 @@
#define EFER_SCE (1 << 0)
/* Page attribute type MSR */
-#define MSR_IA32_PAT 0x277
+#define MSR_IA32_PAT 0x277
+#define MSR_IA32_MPERF 0xe7
+#define MSR_IA32_APERF 0xe8
+#define MSR_IA32_PM_ENABLE 0x770
+#define MSR_IA32_HWP_CAPABILITIES 0x771
+#define MSR_IA32_HWP_REQUEST 0x774
+#define MSR_IA32_HWP_STATUS 0x777
#if defined(__ROMCC__)