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| author | Raul E Rangel <rrangel@chromium.org> | 2020-06-11 16:27:49 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 16:52:58 +0000 |
| commit | 4f5936b45652cea97f964678c93083b0a4f2e478 (patch) | |
| tree | fadca287414f948d07ff2f05983949e8850d4aa4 | |
| parent | 5d0893adced0423241dc016392ca9d4ce1340b2e (diff) | |
| download | coreboot-4f5936b45652cea97f964678c93083b0a4f2e478.tar.xz | |
soc/amd/picasso: Explicitly disable legacy UART
The legacy UARTs are supposed to default to off according to the
documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0
is enabled after reset. The PSP might be enabling it or the documentation
might be wrong.
Having it enabled causes problems though. We have ACPI nodes defining
MMIO UARTs, and the kernel also probes for legacy UARTs. This results in
two drivers accessing the same device, one via MMIO and one via IO. I
suspect this was the cause of the garbage serial output.
Before the change you would see the following in the console:
[ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A
After this change, we no longer see it.
BUG=b:152079780, b:157858890
TEST=Boot trembyle and make sure serial is still working.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 7 | ||||
| -rw-r--r-- | src/soc/amd/picasso/uart.c | 5 |
3 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 5bae754cf6..63c9876fce 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -280,6 +280,7 @@ void southbridge_init(void *chip_info); void fch_pre_init(void); void fch_early_init(void); void set_uart_config(int idx); +void clear_uart_legacy_config(void); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index a18f5a37bd..d2904d894b 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -226,6 +226,13 @@ void fch_pre_init(void) sb_enable_legacy_io(); enable_aoac_devices(); sb_reset_i2c_slaves(); + + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + if (CONFIG(PICASSO_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); } diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 84d6982968..6439efb251 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -38,6 +38,11 @@ uintptr_t uart_platform_base(int idx) return uart_info[idx].base; } +void clear_uart_legacy_config(void) +{ + write16((void *)FCH_UART_LEGACY_DECODE, 0); +} + void set_uart_config(int idx) { uint32_t uart_ctrl; |