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authorMarc Jones <marc.jones@se-eng.com>2012-07-11 16:30:28 -0600
committerRonald G. Minnich <rminnich@gmail.com>2012-11-14 05:37:38 +0100
commit53508fedf8bbd49b10f39a18b3bad6b25b71242e (patch)
tree232d741fc3e732081b2643c8ff72be22a49a32a4
parent48a4a7f24453e8fd0672146d78d7790539c6a2f8 (diff)
downloadcoreboot-53508fedf8bbd49b10f39a18b3bad6b25b71242e.tar.xz
pei_data.h: Fix comment
I added a comment to the pei_data.h to remind users about how the OC pins are mapped. Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/northbridge/intel/sandybridge/pei_data.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 5bb3b38a13..34adddc291 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -79,6 +79,9 @@ struct pei_data
* [1] = overcurrent pin
* [2] = length
*
+ * Ports 0-7 can be mapped to OC0-OC3
+ * Ports 8-13 can be mapped to OC4-OC7
+ *
* Port Length
* MOBILE:
* < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)