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authorFurquan Shaikh <furquan@google.com>2019-04-10 10:09:36 -0700
committerFurquan Shaikh <furquan@google.com>2019-04-12 02:14:24 +0000
commit55208409bc18a9ed6c150bc85e2191bc383e306a (patch)
tree1a3ba2f90b56e21e5de89f2d924f53af5df975a2
parent09b01de336a49e5dbfecf5dad0a2ad8dfe53122c (diff)
downloadcoreboot-55208409bc18a9ed6c150bc85e2191bc383e306a.tar.xz
mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads
This change configures reset config for all pads routed to IOAPIC as PLTRST. This is required to ensure that the internal logic of the GPIO gets reset any time the platform enters S3 or powers off and avoids any interrupt storms on boot-up. BUG=b:129933011 TEST=Verified that there are no interrupt storms on boot-up from S5. Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 0391dfecb0..1c8cfba759 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -20,14 +20,14 @@
static const struct pad_config gpio_table[] = {
/* A0 : SAR0_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A0, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_A0, NONE, PLTRST, LEVEL, NONE),
/* A1 : ESPI_IO0 */
/* A2 : ESPI_IO1 */
/* A3 : ESPI_IO2 */
/* A4 : ESPI_IO3 */
/* A5 : ESPI_CS# */
/* A6 : SAR1_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A6, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_A6, NONE, PLTRST, LEVEL, NONE),
/* A7 : PP3300_SOC_A */
PAD_NC(GPP_A7, NONE),
/* A8 : EMR_GARAGE_DET */
@@ -53,7 +53,7 @@ static const struct pad_config gpio_table[] = {
/* A19 : WWAN_RADIO_DISABLE_1V8_ODL */
PAD_CFG_GPO(GPP_A19, 1, DEEP),
/* A20 : M2_INT_L */
- PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE),
/*
* A21 : TRACKPAD_INT_ODL (wake)
* TODO Combine into single gpio, when ITSS IPCx configuration
@@ -147,7 +147,7 @@ static const struct pad_config gpio_table[] = {
* TODO Configure it back to invert mode, when
* ITSS IPCx configuration is fixed in FSP.
*/
- PAD_CFG_GPI_APIC(GPP_C13, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, NONE),
/* C14 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_C14, 1, DEEP),
/* C15 : WWAN_DPR_SAR_ODL
@@ -171,7 +171,7 @@ static const struct pad_config gpio_table[] = {
* TODO Configure it back to invert mode, when
* ITSS IPCx configuration is fixed in FSP.
*/
- PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE),
/* C22 : EC_IN_RW_OD */
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
/* C23 : WLAN_PE_RST# */
@@ -210,7 +210,7 @@ static const struct pad_config gpio_table[] = {
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
/* D16 : USI_INT */
- PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE),
/* D17 : PCH_HP_SDW_CLK */
PAD_NC(GPP_D17, NONE),
/* D18 : PCH_HP_SDW_DAT */
@@ -457,7 +457,7 @@ static const struct pad_config early_gpio_table[] = {
* TODO Configure it back to invert mode, when
* ITSS IPCx configuration is fixed in FSP.
*/
- PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE),
/* C23 : WLAN_PE_RST# */
PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* F2 : MEM_CH_SEL */