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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-02-26 13:49:56 +0200
committerMarc Jones <marc.jones@se-eng.com>2013-03-07 00:46:32 +0100
commit5a22b14d47955a2cce1d51d883a3c0ee4df39df0 (patch)
treedf61830bce9b395d1b17209305f91a93f9279896
parente988b515f11fa9483fc5209a9894b8d485525a61 (diff)
downloadcoreboot-5a22b14d47955a2cce1d51d883a3c0ee4df39df0.tar.xz
Fix socket LGA775
Models 6ex and 6fx select UDELAY_LAPIC so cannot select contradicting UDELAY_TSC here. Model 1067x requires speedstep. Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/cpu/intel/socket_LGA775/Kconfig1
-rw-r--r--src/cpu/intel/socket_LGA775/Makefile.inc1
2 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index dfb3181096..e5c687a5e6 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -14,7 +14,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_1067X
select MMX
select SSE
- select UDELAY_TSC
select SIPI_VECTOR_IN_ROM
config DCACHE_RAM_SIZE
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index 100b4d8e93..ea68ab1a5c 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -13,5 +13,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc