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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-12-13 17:32:53 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2019-12-27 17:15:19 +0000 |
| commit | 5b9062f3f64b15008aeef5753b477256634933da (patch) | |
| tree | 1364fc6f7b47c3c1daea84e297a5dbb16f9c5a2f | |
| parent | 92bc83674bd5740768c719be2e9402daf9ef27a7 (diff) | |
| download | coreboot-5b9062f3f64b15008aeef5753b477256634933da.tar.xz | |
soc/amd/common: Correct SPI FIFO size check
When checking that command and data fit in the FIFO, don't count the first
byte. The command doesn't go through the FIFO.
TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550
Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_flash.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index d8eeefc7ed..b05c1a4a14 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -40,7 +40,8 @@ int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, siz int ret; u8 buff[SPI_FIFO_DEPTH + 1]; - if ((cmd_len + data_len) > SPI_FIFO_DEPTH) + /* Ensure FIFO is large enough. First byte of command does not go in the FIFO. */ + if ((cmd_len - 1 + data_len) > SPI_FIFO_DEPTH) return -1; memcpy(buff, cmd, cmd_len); memcpy(buff + cmd_len, data, data_len); |