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authorSubrata Banik <subrata.banik@intel.com>2019-06-04 14:43:58 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-06-13 04:39:01 +0000
commit5e5167ed04082e0fe63db865382dc2021877ce3c (patch)
tree109a95e88184e51051de301614c49f8adb5d90b5
parenta0368a0950bbd346b816c4397cfe9e86617d4f77 (diff)
downloadcoreboot-5e5167ed04082e0fe63db865382dc2021877ce3c.tar.xz
mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config. Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb2
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 61b712dbec..112c279fcb 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -28,7 +28,7 @@ chip soc/intel/cannonlake
# Enable System Agent dynamic frequency
register "SaGv" = "SaGv_Enabled"
# Enable heci communication
- register "HeciEnabled" = "1"
+ register "HeciEnabled" = "0"
# Enable Speed Shift Technology support
register "speed_shift_enable" = "1"
# Enable S0ix
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 767df1f795..ce960a74c0 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "HeciEnabled" = "1"
+ register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[2]" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index c96423c93d..739a849715 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "HeciEnabled" = "1"
+ register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[0]" = "1"