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authorJohn Zhao <john.zhao@intel.com>2019-05-23 16:22:21 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-05-29 20:07:26 +0000
commit64fb5aa9c3e50a49d2ecc153ff8c597e203475bc (patch)
tree8fddb316348b4277417feb5ced776ba479053ba5
parent3d90d3bfce7b3e2a885bb4722ecb3a5c127e2882 (diff)
downloadcoreboot-64fb5aa9c3e50a49d2ecc153ff8c597e203475bc.tar.xz
soc/intel/common: Set GSPI clock value to prevent division by zero
Clang Static Analyzer version 8.0.0 detects the division by zero if gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to prevent the division by zero in DIV_ROUND_UP operation. Then the value of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value. TEST=Built and boot up to kernel. Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/soc/intel/common/block/gspi/gspi.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 7fd7d0f9ae..17532bf6db 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -434,9 +434,11 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus)
{
const uint32_t ref_clk_mhz =
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ;
- const uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus);
+ uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus);
+
+ if (!gspi_clk_mhz)
+ gspi_clk_mhz = 1;
- assert(gspi_clk_mhz != 0);
assert(ref_clk_mhz != 0);
return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK;
}