summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeichao Wang <peichao.wang@bitland.corp-partner.google.com>2019-10-15 15:56:02 +0800
committerFurquan Shaikh <furquan@google.com>2019-10-24 21:58:55 +0000
commit65360841632d76f80ef759224a59640dad2b3fd9 (patch)
tree5bd539883313d4283487573361e8d090cf0d1253
parentddd02da1de05761b348c6b8932f5530e3f0d6780 (diff)
downloadcoreboot-65360841632d76f80ef759224a59640dad2b3fd9.tar.xz
mb/google/hatch/var/akemi: Update DPTF thermal sensor for Akemi
Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature BUG=b:143046086 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Philip Chen <philipchen@google.com>
-rw-r--r--src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl131
-rw-r--r--src/mainboard/google/hatch/variants/akemi/overridetree.cb2
2 files changed, 132 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl
index 31f72b3f03..bb46fe9b1c 100644
--- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl
@@ -13,4 +13,133 @@
* GNU General Public License for more details.
*/
-#include <baseboard/acpi/dptf.asl>
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
+#define DPTF_CPU_ACTIVE_AC0 87
+#define DPTF_CPU_ACTIVE_AC1 85
+#define DPTF_CPU_ACTIVE_AC2 83
+#define DPTF_CPU_ACTIVE_AC3 80
+#define DPTF_CPU_ACTIVE_AC4 75
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
+#define DPTF_TSR0_PASSIVE 65
+#define DPTF_TSR0_CRITICAL 75
+#define DPTF_TSR0_ACTIVE_AC0 50
+#define DPTF_TSR0_ACTIVE_AC1 47
+#define DPTF_TSR0_ACTIVE_AC2 45
+#define DPTF_TSR0_ACTIVE_AC3 42
+#define DPTF_TSR0_ACTIVE_AC4 39
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
+#define DPTF_TSR1_PASSIVE 65
+#define DPTF_TSR1_CRITICAL 75
+#define DPTF_TSR1_ACTIVE_AC0 50
+#define DPTF_TSR1_ACTIVE_AC1 47
+#define DPTF_TSR1_ACTIVE_AC2 45
+#define DPTF_TSR1_ACTIVE_AC3 42
+#define DPTF_TSR1_ACTIVE_AC4 39
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU"
+#define DPTF_TSR2_PASSIVE 60
+#define DPTF_TSR2_CRITICAL 75
+#define DPTF_TSR2_ACTIVE_AC0 51
+#define DPTF_TSR2_ACTIVE_AC1 48
+#define DPTF_TSR2_ACTIVE_AC2 45
+#define DPTF_TSR2_ACTIVE_AC3 42
+#define DPTF_TSR2_ACTIVE_AC4 39
+#define DPTF_TSR2_ACTIVE_AC5 36
+#define DPTF_TSR2_ACTIVE_AC6 33
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+})
+
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+ 0, // Revision
+ /*
+ * TODO : Need to update this Table after characterization.
+ * These are initial reference values.
+ */
+ /* Control, Trip Point, Speed, NoiseLevel, Power */
+ Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
+ Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
+ Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
+ Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
+ Package () {50, 0xFFFFFFFF, 3838, 90, 900},
+ Package () {40, 0xFFFFFFFF, 2904, 55, 550},
+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},
+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},
+ Package () {10, 0xFFFFFFFF, 800, 10, 100},
+ Package () {0, 0xFFFFFFFF, 0, 0, 50}
+})
+
+Name (DART, Package () {
+ /* Fan effect on CPU */
+ 0, // Revision
+ Package () {
+ /*
+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+ * AC7, AC8, AC9
+ */
+ \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 80, 70, 60, 50, 40, 30,
+ 0, 0, 0
+ },
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on Ambient (TSR0) */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+
+ /* Charger Throttle Effect on Charger (TSR1) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on CPU (TSR2) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 64000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
index a5fae2beae..51395f9f5c 100644
--- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
@@ -1,4 +1,6 @@
chip soc/intel/cannonlake
+ register "tdp_pl1_override" = "15"
+ register "tdp_pl2_override" = "51"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,