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| author | CK Hu <ck.hu@mediatek.com> | 2020-08-13 14:49:10 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-21 05:59:42 +0000 |
| commit | 693f4a417984849cdb68d176ca162f477275ac3f (patch) | |
| tree | 9de0f2c7666d2cd57d531e16641f154c498f601b | |
| parent | 9bc041187d17c711aa2355e313772b28bdb80eb8 (diff) | |
| download | coreboot-693f4a417984849cdb68d176ca162f477275ac3f.tar.xz | |
mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default value
On MT8192 the SPI flash is actually using a SPI-NOR controller with
its own bus. The number here should be a virtual value as
(SPI_BUS_NUMBER + 1).
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/mainboard/google/asurada/Kconfig | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index e1c96f090c..f5ffb3ccf3 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -41,9 +41,11 @@ config DRIVER_TPM_SPI_BUS hex default 0x0 +# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. +# The number here should be a virtual value as (SPI_BUS_NUMBER + 1). config BOOT_DEVICE_SPI_FLASH_BUS int - default 1 + default 9 config EC_GOOGLE_CHROMEEC_SPI_BUS hex |